Reducing test time via an optimal selection of LFSR feedback taps

Ahmad Afaq, Ali Al-Lawati

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The results of a simulation study demonstrate that in linear feedback shift register-based built-in VLSI testing, the selection of proper feedback taps can reduce the test application time while retaining the testability goals.

Original languageEnglish
Title of host publication6th International Symposium on Signal Processing and Its Applications, ISSPA 2001 - Proceedings; 6 Tutorials in Communications, Image Processing and Signal Analysis
PublisherIEEE Computer Society
Pages300-303
Number of pages4
Volume1
ISBN (Print)0780367030, 9780780367036
DOIs
Publication statusPublished - 2001
Event6th International Symposium on Signal Processing and Its Applications, ISSPA 2001 - Kuala Lumpur, Malaysia
Duration: Aug 13 2001Aug 16 2001

Other

Other6th International Symposium on Signal Processing and Its Applications, ISSPA 2001
CountryMalaysia
CityKuala Lumpur
Period8/13/018/16/01

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ASJC Scopus subject areas

  • Computer Science Applications
  • Signal Processing

Cite this

Afaq, A., & Al-Lawati, A. (2001). Reducing test time via an optimal selection of LFSR feedback taps. In 6th International Symposium on Signal Processing and Its Applications, ISSPA 2001 - Proceedings; 6 Tutorials in Communications, Image Processing and Signal Analysis (Vol. 1, pp. 300-303). [949837] IEEE Computer Society. https://doi.org/10.1109/ISSPA.2001.949837