TY - GEN
T1 - Reducing test time via an optimal selection of LFSR feedback taps
AU - Afaq, Ahmad
AU - Al-Lawati, Ali
PY - 2001
Y1 - 2001
N2 - The results of a simulation study demonstrate that in linear feedback shift register-based built-in VLSI testing, the selection of proper feedback taps can reduce the test application time while retaining the testability goals.
AB - The results of a simulation study demonstrate that in linear feedback shift register-based built-in VLSI testing, the selection of proper feedback taps can reduce the test application time while retaining the testability goals.
UR - http://www.scopus.com/inward/record.url?scp=84904365616&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84904365616&partnerID=8YFLogxK
U2 - 10.1109/ISSPA.2001.949837
DO - 10.1109/ISSPA.2001.949837
M3 - Conference contribution
AN - SCOPUS:84904365616
SN - 0780367030
SN - 9780780367036
T3 - 6th International Symposium on Signal Processing and Its Applications, ISSPA 2001 - Proceedings; 6 Tutorials in Communications, Image Processing and Signal Analysis
SP - 300
EP - 303
BT - 6th International Symposium on Signal Processing and Its Applications, ISSPA 2001 - Proceedings; 6 Tutorials in Communications, Image Processing and Signal Analysis
PB - IEEE Computer Society
T2 - 6th International Symposium on Signal Processing and Its Applications, ISSPA 2001
Y2 - 13 August 2001 through 16 August 2001
ER -