An analytical performance model for the spidergon NoC

Mahmoud Moadeli, Ali Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua

Research output: Chapter in Book/Report/Conference proceedingConference contribution

52 Citations (Scopus)

Abstract

Networks on chip (NoC) emerged as a promising alternative to bus-based interconnect networks to handle the increasing communication requirements of the large systems on chip. Employing an appropriate topology for a NoC is of high importance mainly because it typically trade-offs between cross-cutting concerns such as performance and cost. The spidergon topology is a novel architecture which is proposed recently for NoC domain. The objective of the spidergon NoC has been addressing the need for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [7]. In this paper we analyze the traffic behavior in the spidergon scheme and present an analytical evaluation of the average message latency in the architecture. We prove the validity of the analysis by comparing the model against the results produced by a discreteevent simulator.

Original languageEnglish
Title of host publicationProceedings - International Conference on Advanced Information Networking and Applications, AINA
Pages1014-1021
Number of pages8
DOIs
Publication statusPublished - 2007
Event21st International Conference on Advanced Information Networking and Applications, AINA 2007 - Niagara Falls, ON, Canada
Duration: May 21 2007May 23 2007

Other

Other21st International Conference on Advanced Information Networking and Applications, AINA 2007
CountryCanada
CityNiagara Falls, ON
Period5/21/075/23/07

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Moadeli, M., Shahrabi, A., Vanderbauwhede, W., & Ould-Khaoua, M. (2007). An analytical performance model for the spidergon NoC. In Proceedings - International Conference on Advanced Information Networking and Applications, AINA (pp. 1014-1021). [4221002] https://doi.org/10.1109/AINA.2007.31