An analytical performance model for the spidergon NoC

Mahmoud Moadeli*, Ali Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua

*المؤلف المقابل لهذا العمل

نتاج البحث

54 اقتباسات (Scopus)

ملخص

Networks on chip (NoC) emerged as a promising alternative to bus-based interconnect networks to handle the increasing communication requirements of the large systems on chip. Employing an appropriate topology for a NoC is of high importance mainly because it typically trade-offs between cross-cutting concerns such as performance and cost. The spidergon topology is a novel architecture which is proposed recently for NoC domain. The objective of the spidergon NoC has been addressing the need for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [7]. In this paper we analyze the traffic behavior in the spidergon scheme and present an analytical evaluation of the average message latency in the architecture. We prove the validity of the analysis by comparing the model against the results produced by a discreteevent simulator.

اللغة الأصليةEnglish
عنوان منشور المضيفProceedings - 21st International Conference on Advanced Information Networking and Applications, AINA 2007
الصفحات1014-1021
عدد الصفحات8
المعرِّفات الرقمية للأشياء
حالة النشرPublished - 2007
منشور خارجيًانعم
الحدث21st International Conference on Advanced Information Networking and Applications, AINA 2007 - Niagara Falls, ON
المدة: مايو ٢١ ٢٠٠٧مايو ٢٣ ٢٠٠٧

سلسلة المنشورات

الاسمProceedings - International Conference on Advanced Information Networking and Applications, AINA
رقم المعيار الدولي للدوريات (المطبوع)1550-445X

Other

Other21st International Conference on Advanced Information Networking and Applications, AINA 2007
الدولة/الإقليمCanada
المدينةNiagara Falls, ON
المدة٥/٢١/٠٧٥/٢٣/٠٧

ASJC Scopus subject areas

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