A scalable bandwidth-aware architecture for connected component labeling

Vikram Sampath Kumar, Kevin Irick, Ahmed Al Maashri, Vijaykrishnan Narayanan

Research output: Chapter in Book/Report/Conference proceedingChapter

4 Citations (Scopus)

Abstract

This chapter discusses the design and implementation of a streaming-based Connected Component Labeling architecture. The architecture implements a scalable processor, which can be tuned to match the available I/O bandwidth on the computing platform that hosts the hardware. In addition, the chapter presents the hardware performance measurements when implemented on an FPGA platform.

Original languageEnglish
Title of host publicationVLSI 2010 Annual Symposium
Subtitle of host publicationSelected papers
Pages133-149
Number of pages17
Volume105 LNEE
DOIs
Publication statusPublished - 2011

Publication series

NameLecture Notes in Electrical Engineering
Volume105 LNEE
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

ASJC Scopus subject areas

  • Industrial and Manufacturing Engineering

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  • Cite this

    Kumar, V. S., Irick, K., Maashri, A. A., & Narayanan, V. (2011). A scalable bandwidth-aware architecture for connected component labeling. In VLSI 2010 Annual Symposium: Selected papers (Vol. 105 LNEE, pp. 133-149). (Lecture Notes in Electrical Engineering; Vol. 105 LNEE). https://doi.org/10.1007/978-94-007-1488-5_8