Abstract
This chapter discusses the design and implementation of a streaming-based Connected Component Labeling architecture. The architecture implements a scalable processor, which can be tuned to match the available I/O bandwidth on the computing platform that hosts the hardware. In addition, the chapter presents the hardware performance measurements when implemented on an FPGA platform.
| Original language | English |
|---|---|
| Title of host publication | VLSI 2010 Annual Symposium |
| Subtitle of host publication | Selected papers |
| Pages | 133-149 |
| Number of pages | 17 |
| Volume | 105 LNEE |
| DOIs | |
| Publication status | Published - 2011 |
Publication series
| Name | Lecture Notes in Electrical Engineering |
|---|---|
| Volume | 105 LNEE |
| ISSN (Print) | 1876-1100 |
| ISSN (Electronic) | 1876-1119 |
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ASJC Scopus subject areas
- Industrial and Manufacturing Engineering
Cite this
A scalable bandwidth-aware architecture for connected component labeling. / Kumar, Vikram Sampath; Irick, Kevin; Maashri, Ahmed Al; Narayanan, Vijaykrishnan.
VLSI 2010 Annual Symposium: Selected papers. Vol. 105 LNEE 2011. p. 133-149 (Lecture Notes in Electrical Engineering; Vol. 105 LNEE).Research output: Chapter in Book/Report/Conference proceeding › Chapter
}
TY - CHAP
T1 - A scalable bandwidth-aware architecture for connected component labeling
AU - Kumar, Vikram Sampath
AU - Irick, Kevin
AU - Maashri, Ahmed Al
AU - Narayanan, Vijaykrishnan
PY - 2011
Y1 - 2011
N2 - This chapter discusses the design and implementation of a streaming-based Connected Component Labeling architecture. The architecture implements a scalable processor, which can be tuned to match the available I/O bandwidth on the computing platform that hosts the hardware. In addition, the chapter presents the hardware performance measurements when implemented on an FPGA platform.
AB - This chapter discusses the design and implementation of a streaming-based Connected Component Labeling architecture. The architecture implements a scalable processor, which can be tuned to match the available I/O bandwidth on the computing platform that hosts the hardware. In addition, the chapter presents the hardware performance measurements when implemented on an FPGA platform.
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UR - http://www.scopus.com/inward/citedby.url?scp=84856609182&partnerID=8YFLogxK
U2 - 10.1007/978-94-007-1488-5_8
DO - 10.1007/978-94-007-1488-5_8
M3 - Chapter
SN - 9789400714878
VL - 105 LNEE
T3 - Lecture Notes in Electrical Engineering
SP - 133
EP - 149
BT - VLSI 2010 Annual Symposium
ER -