This chapter discusses the design and implementation of a streaming-based Connected Component Labeling architecture. The architecture implements a scalable processor, which can be tuned to match the available I/O bandwidth on the computing platform that hosts the hardware. In addition, the chapter presents the hardware performance measurements when implemented on an FPGA platform.
|Title of host publication||VLSI 2010 Annual Symposium|
|Subtitle of host publication||Selected papers|
|Number of pages||17|
|Publication status||Published - 2011|
|Name||Lecture Notes in Electrical Engineering|
ASJC Scopus subject areas
- Industrial and Manufacturing Engineering