TY - CHAP
T1 - A scalable bandwidth-aware architecture for connected component labeling
AU - Kumar, Vikram Sampath
AU - Irick, Kevin
AU - Maashri, Ahmed Al
AU - Narayanan, Vijaykrishnan
N1 - Funding Information:
This work was supported in part by NSF awards #0702617 & #0916887, and a scholarship funding from the Government of the Sultanate of Oman.
PY - 2011
Y1 - 2011
N2 - This chapter discusses the design and implementation of a streaming-based Connected Component Labeling architecture. The architecture implements a scalable processor, which can be tuned to match the available I/O bandwidth on the computing platform that hosts the hardware. In addition, the chapter presents the hardware performance measurements when implemented on an FPGA platform.
AB - This chapter discusses the design and implementation of a streaming-based Connected Component Labeling architecture. The architecture implements a scalable processor, which can be tuned to match the available I/O bandwidth on the computing platform that hosts the hardware. In addition, the chapter presents the hardware performance measurements when implemented on an FPGA platform.
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U2 - 10.1007/978-94-007-1488-5_8
DO - 10.1007/978-94-007-1488-5_8
M3 - Chapter
AN - SCOPUS:84856609182
SN - 9789400714878
T3 - Lecture Notes in Electrical Engineering
SP - 133
EP - 149
BT - VLSI 2010 Annual Symposium
A2 - Voros, Nikolaos
A2 - Mukherjee, Amar
A2 - Sklavos, Nicolas
A2 - Masselos, Konstantinos
A2 - Huebner, Michael
ER -