TY - JOUR
T1 - Performance enhancement of multicore architecture
AU - Awadalla, Medhat
AU - Konsowa, Hanan
N1 - Publisher Copyright:
Copyright © 2015 Institute of Advanced Engineering and Science. All rights reserved.
PY - 2015/8/1
Y1 - 2015/8/1
N2 - Multicore processors integrate several cores on a single chip. The fixed architecture of multicore platforms often fails to accommodate the inherent diverse requirements of different applications. The permanent need to enhance the performance of multicore architecture motivates the development of a dynamic architecture. To address this issue, this paper presents new algorithms for thread selection in fetch stage. Moreover, this paper presents three new fetch stage policies, EACH-LOOP-FETCH, INC-FETCH, and WZ-FETCH, based on Ordinary Least Square (OLS) regression statistic method. These new fetch policies differ on thread selection time which is represented by instructions' count and window size. Furthermore, the simulation multicore tool, is adapted to cope with multicore processor dynamic design by adding a dynamic feature in the policy of thread selection in fetch stage. SPLASH2, parallel scientific workloads, has been used to validate the proposed adaptation for multi2sim. Intensive simulated experiments have been conducted and the obtained results show that remarkable performance enhancements have been achieved in terms of execution time and number of instructions per second. produces less broadcast operations compared to the typical algorithm.
AB - Multicore processors integrate several cores on a single chip. The fixed architecture of multicore platforms often fails to accommodate the inherent diverse requirements of different applications. The permanent need to enhance the performance of multicore architecture motivates the development of a dynamic architecture. To address this issue, this paper presents new algorithms for thread selection in fetch stage. Moreover, this paper presents three new fetch stage policies, EACH-LOOP-FETCH, INC-FETCH, and WZ-FETCH, based on Ordinary Least Square (OLS) regression statistic method. These new fetch policies differ on thread selection time which is represented by instructions' count and window size. Furthermore, the simulation multicore tool, is adapted to cope with multicore processor dynamic design by adding a dynamic feature in the policy of thread selection in fetch stage. SPLASH2, parallel scientific workloads, has been used to validate the proposed adaptation for multi2sim. Intensive simulated experiments have been conducted and the obtained results show that remarkable performance enhancements have been achieved in terms of execution time and number of instructions per second. produces less broadcast operations compared to the typical algorithm.
KW - Fetch policy
KW - Multi2sim
KW - Multicore
KW - Ordinary Least Square (OLS)
KW - Pipeline processor
UR - http://www.scopus.com/inward/record.url?scp=84938579819&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84938579819&partnerID=8YFLogxK
U2 - 10.11591/ijece.v5i4.pp669-684
DO - 10.11591/ijece.v5i4.pp669-684
M3 - Article
AN - SCOPUS:84938579819
SN - 2088-8708
VL - 5
SP - 669
EP - 684
JO - International Journal of Electrical and Computer Engineering
JF - International Journal of Electrical and Computer Engineering
IS - 4
ER -