TY - GEN
T1 - How to design an effective Serial Input Shift Register (SISR) for data compression process of built-in self-test methodology
AU - Ahmad, A.
AU - Jaber, Al Balushi
PY - 2009
Y1 - 2009
N2 - This paper investigates the impact of characteristic polynomial on an effective design of Serial Input Shift Register (SISR). How the use of a primitive characteristic polynomial cannot cope with the minimization of aliasing error probability. Further, the paper also, suggests about the selection of characteristic polynomial to minimize hardware, power dissipation and test data compression time. The study of this paper is based on simulation study using a suitably developed tool.
AB - This paper investigates the impact of characteristic polynomial on an effective design of Serial Input Shift Register (SISR). How the use of a primitive characteristic polynomial cannot cope with the minimization of aliasing error probability. Further, the paper also, suggests about the selection of characteristic polynomial to minimize hardware, power dissipation and test data compression time. The study of this paper is based on simulation study using a suitably developed tool.
KW - Aliasing error
KW - Built-in self-test
KW - Characteristic polynomial
KW - Circuit under test
KW - Design for testability
KW - Linear feedback shift registers
KW - Primitive polynomial
KW - Serial input shift register
KW - System on chip
UR - http://www.scopus.com/inward/record.url?scp=77950413347&partnerID=8YFLogxK
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U2 - 10.1109/IDT.2009.5404091
DO - 10.1109/IDT.2009.5404091
M3 - Conference contribution
AN - SCOPUS:77950413347
SN - 9781424457489
T3 - 2009 4th International Design and Test Workshop, IDT 2009
BT - 2009 4th International Design and Test Workshop, IDT 2009
T2 - 2009 4th International Design and Test Workshop, IDT 2009
Y2 - 15 November 2009 through 17 November 2009
ER -