How to design an effective Serial Input Shift Register (SISR) for data compression process of built-in self-test methodology

A. Ahmad, Al Balushi Jaber

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper investigates the impact of characteristic polynomial on an effective design of Serial Input Shift Register (SISR). How the use of a primitive characteristic polynomial cannot cope with the minimization of aliasing error probability. Further, the paper also, suggests about the selection of characteristic polynomial to minimize hardware, power dissipation and test data compression time. The study of this paper is based on simulation study using a suitably developed tool.

Original languageEnglish
Title of host publication2009 4th International Design and Test Workshop, IDT 2009
DOIs
Publication statusPublished - 2009
Event2009 4th International Design and Test Workshop, IDT 2009 - Riyadh, Saudi Arabia
Duration: Nov 15 2009Nov 17 2009

Other

Other2009 4th International Design and Test Workshop, IDT 2009
CountrySaudi Arabia
CityRiyadh
Period11/15/0911/17/09

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Keywords

  • Aliasing error
  • Built-in self-test
  • Characteristic polynomial
  • Circuit under test
  • Design for testability
  • Linear feedback shift registers
  • Primitive polynomial
  • Serial input shift register
  • System on chip

ASJC Scopus subject areas

  • Computer Science(all)
  • Control and Systems Engineering

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