Design and implementation of a nibble-size multiplier for (-1+j)-base complex binary numbers

Complex binary number system is unique, concise, one-unit notation for representing complex numbers in binary number system with base-(-l+j). With the procedure for arithmetic operations involving complex binary numbers already established, in this paper, we have presented design of a decoder-based minimum-delay multiplier circuit for nibble-sized complex binary numbers and implemented it on various Xilinx FPGAs.