Design and implementation of a nibble-size multiplier for (-1+j)-base complex binary numbers

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Abstract

Complex binary number system is unique, concise, one-unit notation for representing complex numbers in binary number system with base-(-l+j). With the procedure for arithmetic operations involving complex binary numbers already established, in this paper, we have presented design of a decoder-based minimum-delay multiplier circuit for nibble-sized complex binary numbers and implemented it on various Xilinx FPGAs.

Original languageEnglish
Pages (from-to)1539-1544
Number of pages6
JournalWSEAS Transactions on Circuits and Systems
Volume4
Issue number11
Publication statusPublished - Nov 2005

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Keywords

  • Arithmetic circuits
  • Complex binary number
  • Computer arithmetic
  • Decoder
  • FPGA
  • Multiplier

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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