Bit Swapped Test Technique with Statistical Signal Properties for EVS Applications

Keynote/Invited talk: The intent of this talk is to introduce the idea of a new scheme devised to reduce test power, with employment of a low-transition test pattern generator. Various techniques have been proposed to reduce the test power such as Bit Insertion, Bit swapping. In the proposed scheme, Bit Swapping technique is integrated with pseudorandom signal analyzer to make the further reduction in the test power. A hardware complexity estimation for testing Embedded Vision Systems (EVS) will also be discussed.