Abstract
This paper presents a new algorithmic procedure for testing the feedback connections of an LFSR to check whether the design may generate maximal length sequences (m-sequence) or not. Since for an n-bit LFSR the algorithm only requires an (n-1) - bit register operation through out its entire implementation thus, it requires minimal CPU time as well as memory space. Therefore, the attribute of the developed algorithm is two folded. The first, it is the fastest available algorithm and secondly, it is not posing the restriction on the length of the LFSRs like other existing methods. The simulation result of the algorithm is compared with the results of existing algorithms and found much faster than the other existing algorithms. The implementation procedure of the algorithm is demonstrated through an elaborative example.
| Original language | English |
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| Title of host publication | IEEE Region 10 International Conference on Electrical and Electronic Technology |
| Editors | D. Tien, Y.C. Liang, D. Tien, Y.C. Liang |
| Pages | 366-369 |
| Number of pages | 4 |
| Publication status | Published - 2001 |
| Event | IEEE Region 10 International Conference on Electrical and Electronic Technology - Singapore, Singapore Duration: Aug 19 2001 → Aug 22 2001 |
Other
| Other | IEEE Region 10 International Conference on Electrical and Electronic Technology |
|---|---|
| Country | Singapore |
| City | Singapore |
| Period | 8/19/01 → 8/22/01 |
Keywords
- Feedback connections
- LFSR
- M-sequence
- Primitive polynomial
ASJC Scopus subject areas
- Engineering(all)