Investigation of some quite interesting divisibility situations in a signature analyzer implementation

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4 Citations (Scopus)

Abstract

When designing error detecting and correcting systems, cryptographic apparatus, scramblers and other secure, safe and authenticated communication and digital system response data compression devices, the division of polynomials are frequently involved. Commonly, the process of division is implemented by using hardware known as Linear Feedback Shift Registers (LFSRs). In digital system testing the technique of Built-In Self Test (BIST) uses this LFSR based division process for response data compression and is popularly known as Signature Analyzer (SA). This paper presents a simulation experiment on the effectiveness study of the SA schemes. The finding of the results of the simulation study reveals that in SA implementation; in general the uses of primitive characteristic polynomials are the best. However, the study further investigates that the use of some critical primitive characteristic polynomials may reverse the effectiveness of the SA schemes i.e. lead to observe maximum aliasing errors.

Original languageEnglish
Pages (from-to)299-308
Number of pages10
JournalWSEAS Transactions on Circuits and Systems
Volume10
Issue number9
Publication statusPublished - Sep 2011

Fingerprint

Shift registers
Data compression
Polynomials
Feedback
Built-in self test
Computer hardware
Communication
Testing
Experiments

Keywords

  • Aliasing errors
  • Built-in self-test
  • Characteristic polynomial
  • Cyclic redundancy check
  • Linear Feedback Shift Registers
  • Polynomial division
  • Primitive polynomials
  • Signature analyzer
  • Vlsi

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

@article{25083d982a1347cba5079ee94b4554c0,
title = "Investigation of some quite interesting divisibility situations in a signature analyzer implementation",
abstract = "When designing error detecting and correcting systems, cryptographic apparatus, scramblers and other secure, safe and authenticated communication and digital system response data compression devices, the division of polynomials are frequently involved. Commonly, the process of division is implemented by using hardware known as Linear Feedback Shift Registers (LFSRs). In digital system testing the technique of Built-In Self Test (BIST) uses this LFSR based division process for response data compression and is popularly known as Signature Analyzer (SA). This paper presents a simulation experiment on the effectiveness study of the SA schemes. The finding of the results of the simulation study reveals that in SA implementation; in general the uses of primitive characteristic polynomials are the best. However, the study further investigates that the use of some critical primitive characteristic polynomials may reverse the effectiveness of the SA schemes i.e. lead to observe maximum aliasing errors.",
keywords = "Aliasing errors, Built-in self-test, Characteristic polynomial, Cyclic redundancy check, Linear Feedback Shift Registers, Polynomial division, Primitive polynomials, Signature analyzer, Vlsi",
author = "Afaq Ahmad",
year = "2011",
month = "9",
language = "English",
volume = "10",
pages = "299--308",
journal = "WSEAS Transactions on Circuits and Systems",
issn = "1109-2734",
publisher = "World Scientific and Engineering Academy and Society",
number = "9",

}

TY - JOUR

T1 - Investigation of some quite interesting divisibility situations in a signature analyzer implementation

AU - Ahmad, Afaq

PY - 2011/9

Y1 - 2011/9

N2 - When designing error detecting and correcting systems, cryptographic apparatus, scramblers and other secure, safe and authenticated communication and digital system response data compression devices, the division of polynomials are frequently involved. Commonly, the process of division is implemented by using hardware known as Linear Feedback Shift Registers (LFSRs). In digital system testing the technique of Built-In Self Test (BIST) uses this LFSR based division process for response data compression and is popularly known as Signature Analyzer (SA). This paper presents a simulation experiment on the effectiveness study of the SA schemes. The finding of the results of the simulation study reveals that in SA implementation; in general the uses of primitive characteristic polynomials are the best. However, the study further investigates that the use of some critical primitive characteristic polynomials may reverse the effectiveness of the SA schemes i.e. lead to observe maximum aliasing errors.

AB - When designing error detecting and correcting systems, cryptographic apparatus, scramblers and other secure, safe and authenticated communication and digital system response data compression devices, the division of polynomials are frequently involved. Commonly, the process of division is implemented by using hardware known as Linear Feedback Shift Registers (LFSRs). In digital system testing the technique of Built-In Self Test (BIST) uses this LFSR based division process for response data compression and is popularly known as Signature Analyzer (SA). This paper presents a simulation experiment on the effectiveness study of the SA schemes. The finding of the results of the simulation study reveals that in SA implementation; in general the uses of primitive characteristic polynomials are the best. However, the study further investigates that the use of some critical primitive characteristic polynomials may reverse the effectiveness of the SA schemes i.e. lead to observe maximum aliasing errors.

KW - Aliasing errors

KW - Built-in self-test

KW - Characteristic polynomial

KW - Cyclic redundancy check

KW - Linear Feedback Shift Registers

KW - Polynomial division

KW - Primitive polynomials

KW - Signature analyzer

KW - Vlsi

UR - http://www.scopus.com/inward/record.url?scp=84555218003&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84555218003&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:84555218003

VL - 10

SP - 299

EP - 308

JO - WSEAS Transactions on Circuits and Systems

JF - WSEAS Transactions on Circuits and Systems

SN - 1109-2734

IS - 9

ER -