Efficient architecture and implementation of vector median filter in Co-Design context

Anis Boudabous, Lazhar Khriji, A. Ben Atitallah, P. Kadionik, Nouri Masmoudi

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This work presents an efficient fast parallel architecture of the Vector Median Filter (VMF) using combined hardware/software (HW/SW) implementation. The hardware part of the system is implemented using VHDL language, whereas the software part is developed using C/C++ language. The software part of the embedded system uses the NIOS-II softcore processor and the operating system used is μClinux. The comparison between the software and HW/SW solutions shows that adding a hardware part in the design attempts to speed up the filtering process compared to the software solution. This efficient embedded system implementation can perform well in several image processing applications.

Original languageEnglish
Pages (from-to)113-119
Number of pages7
JournalRadioengineering
Volume16
Issue number3
Publication statusPublished - 2007

Keywords

  • Color image
  • FPGA
  • NIOS-II
  • SoPC
  • VMF

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Boudabous, A., Khriji, L., Ben Atitallah, A., Kadionik, P., & Masmoudi, N. (2007). Efficient architecture and implementation of vector median filter in Co-Design context. Radioengineering, 16(3), 113-119.