Efficient architecture and implementation of vector median filter in Co-Design context

Anis Boudabous, Lazhar Khriji, A. Ben Atitallah, P. Kadionik, Nouri Masmoudi

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This work presents an efficient fast parallel architecture of the Vector Median Filter (VMF) using combined hardware/software (HW/SW) implementation. The hardware part of the system is implemented using VHDL language, whereas the software part is developed using C/C++ language. The software part of the embedded system uses the NIOS-II softcore processor and the operating system used is μClinux. The comparison between the software and HW/SW solutions shows that adding a hardware part in the design attempts to speed up the filtering process compared to the software solution. This efficient embedded system implementation can perform well in several image processing applications.

Original languageEnglish
Pages (from-to)113-119
Number of pages7
JournalRadioengineering
Volume16
Issue number3
Publication statusPublished - 2007

Fingerprint

Median filters
Hardware
Embedded systems
Computer hardware description languages
Parallel architectures
Image processing

Keywords

  • Color image
  • FPGA
  • NIOS-II
  • SoPC
  • VMF

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Boudabous, A., Khriji, L., Ben Atitallah, A., Kadionik, P., & Masmoudi, N. (2007). Efficient architecture and implementation of vector median filter in Co-Design context. Radioengineering, 16(3), 113-119.

Efficient architecture and implementation of vector median filter in Co-Design context. / Boudabous, Anis; Khriji, Lazhar; Ben Atitallah, A.; Kadionik, P.; Masmoudi, Nouri.

In: Radioengineering, Vol. 16, No. 3, 2007, p. 113-119.

Research output: Contribution to journalArticle

Boudabous, A, Khriji, L, Ben Atitallah, A, Kadionik, P & Masmoudi, N 2007, 'Efficient architecture and implementation of vector median filter in Co-Design context', Radioengineering, vol. 16, no. 3, pp. 113-119.
Boudabous A, Khriji L, Ben Atitallah A, Kadionik P, Masmoudi N. Efficient architecture and implementation of vector median filter in Co-Design context. Radioengineering. 2007;16(3):113-119.
Boudabous, Anis ; Khriji, Lazhar ; Ben Atitallah, A. ; Kadionik, P. ; Masmoudi, Nouri. / Efficient architecture and implementation of vector median filter in Co-Design context. In: Radioengineering. 2007 ; Vol. 16, No. 3. pp. 113-119.
@article{413817065a7648fca58bf2e22027d274,
title = "Efficient architecture and implementation of vector median filter in Co-Design context",
abstract = "This work presents an efficient fast parallel architecture of the Vector Median Filter (VMF) using combined hardware/software (HW/SW) implementation. The hardware part of the system is implemented using VHDL language, whereas the software part is developed using C/C++ language. The software part of the embedded system uses the NIOS-II softcore processor and the operating system used is μClinux. The comparison between the software and HW/SW solutions shows that adding a hardware part in the design attempts to speed up the filtering process compared to the software solution. This efficient embedded system implementation can perform well in several image processing applications.",
keywords = "Color image, FPGA, NIOS-II, SoPC, VMF",
author = "Anis Boudabous and Lazhar Khriji and {Ben Atitallah}, A. and P. Kadionik and Nouri Masmoudi",
year = "2007",
language = "English",
volume = "16",
pages = "113--119",
journal = "Radioengineering",
issn = "1210-2512",
publisher = "Czech Technical University",
number = "3",

}

TY - JOUR

T1 - Efficient architecture and implementation of vector median filter in Co-Design context

AU - Boudabous, Anis

AU - Khriji, Lazhar

AU - Ben Atitallah, A.

AU - Kadionik, P.

AU - Masmoudi, Nouri

PY - 2007

Y1 - 2007

N2 - This work presents an efficient fast parallel architecture of the Vector Median Filter (VMF) using combined hardware/software (HW/SW) implementation. The hardware part of the system is implemented using VHDL language, whereas the software part is developed using C/C++ language. The software part of the embedded system uses the NIOS-II softcore processor and the operating system used is μClinux. The comparison between the software and HW/SW solutions shows that adding a hardware part in the design attempts to speed up the filtering process compared to the software solution. This efficient embedded system implementation can perform well in several image processing applications.

AB - This work presents an efficient fast parallel architecture of the Vector Median Filter (VMF) using combined hardware/software (HW/SW) implementation. The hardware part of the system is implemented using VHDL language, whereas the software part is developed using C/C++ language. The software part of the embedded system uses the NIOS-II softcore processor and the operating system used is μClinux. The comparison between the software and HW/SW solutions shows that adding a hardware part in the design attempts to speed up the filtering process compared to the software solution. This efficient embedded system implementation can perform well in several image processing applications.

KW - Color image

KW - FPGA

KW - NIOS-II

KW - SoPC

KW - VMF

UR - http://www.scopus.com/inward/record.url?scp=79953322194&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79953322194&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:79953322194

VL - 16

SP - 113

EP - 119

JO - Radioengineering

JF - Radioengineering

SN - 1210-2512

IS - 3

ER -