The networks employed in multicomputer architectures share many characteristics with those encountered at larger scales, but the specific requirement of interprocessor communication introduces some additional special considerations. The structures are typically regular, and performance is usually the key design objective. This paper first provides a general outline of research into the comparative performance analysis of these systems, examining the impact of topology, switching, and routing techniques under different types of traffic load. Using a combination of mathematical modeling and discrete event simulation, issues such as the bandwidth constraints and switching delays imposed by potential implementation technologies have been taken into account. By way of illustration, the paper concludes with a brief description of a recently developed queuing model for adaptive routing in k-ary n-cube networks.
|Number of pages||16|
|Journal||International Journal of High Performance Computing Applications|
|Publication status||Published - Sep 2000|
ASJC Scopus subject areas
- Theoretical Computer Science
- Hardware and Architecture