Communication modelling of the spidergon NoC with virtual channels

M. Moadeli, A. Shahrabi, W. Vanderbauwhede, M. Ould-Khaoua

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

The spidergon scheme is a commercial NoC (Network On-Chip) proposed recently to address the demand for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [12]. The increasing diversity of the applications quality of service requirements may, however, inhibit employing a particular architecture for a wide range of applications, unless the performance it delivers is improved. A traditional approach to enhance the performance of the interconnect networks has been employing the virtual channels. In this paper, we present an analytical model to evaluate the performance of the spidergon NoC and to study the effect of employing virtual channels. Results obtained through simulation experiments show that the model exhibits a good degree of accuracy in predicting average message latency under various working conditions.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
DOIs
Publication statusPublished - 2007
Event36th International Conference on Parallel Processing in Xi'an, ICPP - Xi'an, China
Duration: Sep 10 2007Sep 14 2007

Other

Other36th International Conference on Parallel Processing in Xi'an, ICPP
CountryChina
CityXi'an
Period9/10/079/14/07

Fingerprint

Communication
Analytical models
Quality of service
Topology
Costs
Experiments
Network-on-chip
System-on-chip

ASJC Scopus subject areas

  • Hardware and Architecture
  • Engineering(all)

Cite this

Moadeli, M., Shahrabi, A., Vanderbauwhede, W., & Ould-Khaoua, M. (2007). Communication modelling of the spidergon NoC with virtual channels. In Proceedings of the International Conference on Parallel Processing [4343883] https://doi.org/10.1109/ICPP.2007.28

Communication modelling of the spidergon NoC with virtual channels. / Moadeli, M.; Shahrabi, A.; Vanderbauwhede, W.; Ould-Khaoua, M.

Proceedings of the International Conference on Parallel Processing. 2007. 4343883.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Moadeli, M, Shahrabi, A, Vanderbauwhede, W & Ould-Khaoua, M 2007, Communication modelling of the spidergon NoC with virtual channels. in Proceedings of the International Conference on Parallel Processing., 4343883, 36th International Conference on Parallel Processing in Xi'an, ICPP, Xi'an, China, 9/10/07. https://doi.org/10.1109/ICPP.2007.28
Moadeli M, Shahrabi A, Vanderbauwhede W, Ould-Khaoua M. Communication modelling of the spidergon NoC with virtual channels. In Proceedings of the International Conference on Parallel Processing. 2007. 4343883 https://doi.org/10.1109/ICPP.2007.28
Moadeli, M. ; Shahrabi, A. ; Vanderbauwhede, W. ; Ould-Khaoua, M. / Communication modelling of the spidergon NoC with virtual channels. Proceedings of the International Conference on Parallel Processing. 2007.
@inproceedings{9aa1431795a64c60bebcbbffb6285dac,
title = "Communication modelling of the spidergon NoC with virtual channels",
abstract = "The spidergon scheme is a commercial NoC (Network On-Chip) proposed recently to address the demand for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [12]. The increasing diversity of the applications quality of service requirements may, however, inhibit employing a particular architecture for a wide range of applications, unless the performance it delivers is improved. A traditional approach to enhance the performance of the interconnect networks has been employing the virtual channels. In this paper, we present an analytical model to evaluate the performance of the spidergon NoC and to study the effect of employing virtual channels. Results obtained through simulation experiments show that the model exhibits a good degree of accuracy in predicting average message latency under various working conditions.",
author = "M. Moadeli and A. Shahrabi and W. Vanderbauwhede and M. Ould-Khaoua",
year = "2007",
doi = "10.1109/ICPP.2007.28",
language = "English",
isbn = "076952933X",
booktitle = "Proceedings of the International Conference on Parallel Processing",

}

TY - GEN

T1 - Communication modelling of the spidergon NoC with virtual channels

AU - Moadeli, M.

AU - Shahrabi, A.

AU - Vanderbauwhede, W.

AU - Ould-Khaoua, M.

PY - 2007

Y1 - 2007

N2 - The spidergon scheme is a commercial NoC (Network On-Chip) proposed recently to address the demand for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [12]. The increasing diversity of the applications quality of service requirements may, however, inhibit employing a particular architecture for a wide range of applications, unless the performance it delivers is improved. A traditional approach to enhance the performance of the interconnect networks has been employing the virtual channels. In this paper, we present an analytical model to evaluate the performance of the spidergon NoC and to study the effect of employing virtual channels. Results obtained through simulation experiments show that the model exhibits a good degree of accuracy in predicting average message latency under various working conditions.

AB - The spidergon scheme is a commercial NoC (Network On-Chip) proposed recently to address the demand for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [12]. The increasing diversity of the applications quality of service requirements may, however, inhibit employing a particular architecture for a wide range of applications, unless the performance it delivers is improved. A traditional approach to enhance the performance of the interconnect networks has been employing the virtual channels. In this paper, we present an analytical model to evaluate the performance of the spidergon NoC and to study the effect of employing virtual channels. Results obtained through simulation experiments show that the model exhibits a good degree of accuracy in predicting average message latency under various working conditions.

UR - http://www.scopus.com/inward/record.url?scp=47249125808&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=47249125808&partnerID=8YFLogxK

U2 - 10.1109/ICPP.2007.28

DO - 10.1109/ICPP.2007.28

M3 - Conference contribution

SN - 076952933X

SN - 9780769529332

BT - Proceedings of the International Conference on Parallel Processing

ER -