Communication modelling of the spidergon NoC with virtual channels

M. Moadeli*, A. Shahrabi, W. Vanderbauwhede, M. Ould-Khaoua

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (SciVal)


The spidergon scheme is a commercial NoC (Network On-Chip) proposed recently to address the demand for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [12]. The increasing diversity of the applications quality of service requirements may, however, inhibit employing a particular architecture for a wide range of applications, unless the performance it delivers is improved. A traditional approach to enhance the performance of the interconnect networks has been employing the virtual channels. In this paper, we present an analytical model to evaluate the performance of the spidergon NoC and to study the effect of employing virtual channels. Results obtained through simulation experiments show that the model exhibits a good degree of accuracy in predicting average message latency under various working conditions.

Original languageEnglish
Title of host publication2007 International Conference on Parallel Processing, ICPP
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages1
ISBN (Print)076952933X, 9780769529332
Publication statusPublished - 2007
Event36th International Conference on Parallel Processing in Xi'an, ICPP - Xi'an, China
Duration: Sept 10 2007Sept 14 2007

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918


Other36th International Conference on Parallel Processing in Xi'an, ICPP

ASJC Scopus subject areas

  • Hardware and Architecture
  • Engineering(all)


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