Abstract
The spidergon scheme is a commercial NoC (Network On-Chip) proposed recently to address the demand for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [12]. The increasing diversity of the applications quality of service requirements may, however, inhibit employing a particular architecture for a wide range of applications, unless the performance it delivers is improved. A traditional approach to enhance the performance of the interconnect networks has been employing the virtual channels. In this paper, we present an analytical model to evaluate the performance of the spidergon NoC and to study the effect of employing virtual channels. Results obtained through simulation experiments show that the model exhibits a good degree of accuracy in predicting average message latency under various working conditions.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the International Conference on Parallel Processing |
| DOIs | |
| Publication status | Published - 2007 |
| Event | 36th International Conference on Parallel Processing in Xi'an, ICPP - Xi'an, China Duration: Sep 10 2007 → Sep 14 2007 |
Other
| Other | 36th International Conference on Parallel Processing in Xi'an, ICPP |
|---|---|
| Country | China |
| City | Xi'an |
| Period | 9/10/07 → 9/14/07 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Engineering(all)
Cite this
Communication modelling of the spidergon NoC with virtual channels. / Moadeli, M.; Shahrabi, A.; Vanderbauwhede, W.; Ould-Khaoua, M.
Proceedings of the International Conference on Parallel Processing. 2007. 4343883.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Communication modelling of the spidergon NoC with virtual channels
AU - Moadeli, M.
AU - Shahrabi, A.
AU - Vanderbauwhede, W.
AU - Ould-Khaoua, M.
PY - 2007
Y1 - 2007
N2 - The spidergon scheme is a commercial NoC (Network On-Chip) proposed recently to address the demand for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [12]. The increasing diversity of the applications quality of service requirements may, however, inhibit employing a particular architecture for a wide range of applications, unless the performance it delivers is improved. A traditional approach to enhance the performance of the interconnect networks has been employing the virtual channels. In this paper, we present an analytical model to evaluate the performance of the spidergon NoC and to study the effect of employing virtual channels. Results obtained through simulation experiments show that the model exhibits a good degree of accuracy in predicting average message latency under various working conditions.
AB - The spidergon scheme is a commercial NoC (Network On-Chip) proposed recently to address the demand for a fixed and optimized topology to realize cost effective multi-processor SoC (MPSoC) development [12]. The increasing diversity of the applications quality of service requirements may, however, inhibit employing a particular architecture for a wide range of applications, unless the performance it delivers is improved. A traditional approach to enhance the performance of the interconnect networks has been employing the virtual channels. In this paper, we present an analytical model to evaluate the performance of the spidergon NoC and to study the effect of employing virtual channels. Results obtained through simulation experiments show that the model exhibits a good degree of accuracy in predicting average message latency under various working conditions.
UR - http://www.scopus.com/inward/record.url?scp=47249125808&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=47249125808&partnerID=8YFLogxK
U2 - 10.1109/ICPP.2007.28
DO - 10.1109/ICPP.2007.28
M3 - Conference contribution
SN - 076952933X
SN - 9780769529332
BT - Proceedings of the International Conference on Parallel Processing
ER -