Abstract
We consider two flow control schemes for Best Effort traffic in on-chip architectures, which can be deemed as the solutions to the boundary extremes of a class of utility maximization problem. At one extreme, we consider the so-called Rate-Sum flow control scheme, which aims at improving the performance of the underlying system by roughly maximizing throughput while satisfying capacity constraints. At the other extreme, we deem the Max-Min flow control, whose concern is to maintain Max-Min fairness in rate allocation by fairly sacrificing the throughput. We then elaborate our argument through a weighting mechanism in order to achieve a balance between the orthogonal goals of performance and fairness. Moreover, we investigate the implementation facets of the presented flow control schemes in on-chip architectures. Finally, we validate the proposed flow control schemes and the subsequent arguments through extensive simulation experiments.
Original language | English |
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Title of host publication | IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium |
DOIs | |
Publication status | Published - 2009 |
Event | 23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009 - Rome, Italy Duration: May 23 2009 → May 29 2009 |
Other
Other | 23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009 |
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Country | Italy |
City | Rome |
Period | 5/23/09 → 5/29/09 |
ASJC Scopus subject areas
- Computational Theory and Mathematics
- Hardware and Architecture
- Software