Abstract
We consider two flow control schemes for Best Effort traffic in on-chip architectures, which can be deemed as the solutions to the boundary extremes of a class of utility maximization problem. At one extreme, we consider the so-called Rate-Sum flow control scheme, which aims at improving the performance of the underlying system by roughly maximizing throughput while satisfying capacity constraints. At the other extreme, we deem the Max-Min flow control, whose concern is to maintain Max-Min fairness in rate allocation by fairly sacrificing the throughput. We then elaborate our argument through a weighting mechanism in order to achieve a balance between the orthogonal goals of performance and fairness. Moreover, we investigate the implementation facets of the presented flow control schemes in on-chip architectures. Finally, we validate the proposed flow control schemes and the subsequent arguments through extensive simulation experiments.
| Original language | English |
|---|---|
| Title of host publication | IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium |
| DOIs | |
| Publication status | Published - 2009 |
| Event | 23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009 - Rome, Italy Duration: May 23 2009 → May 29 2009 |
Other
| Other | 23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009 |
|---|---|
| Country | Italy |
| City | Rome |
| Period | 5/23/09 → 5/29/09 |
Fingerprint
ASJC Scopus subject areas
- Computational Theory and Mathematics
- Hardware and Architecture
- Software
Cite this
Throughput-fairness tradeoff in best effort flow control for on-chip architectures. / Jafari, Fahimeh; Talebi, Mohammad S.; Yaghmaee, Mohammad H.; Khonsari, Ahmad; Ould-Khaoua, Mohamed.
IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 2009. 5161186.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Throughput-fairness tradeoff in best effort flow control for on-chip architectures
AU - Jafari, Fahimeh
AU - Talebi, Mohammad S.
AU - Yaghmaee, Mohammad H.
AU - Khonsari, Ahmad
AU - Ould-Khaoua, Mohamed
PY - 2009
Y1 - 2009
N2 - We consider two flow control schemes for Best Effort traffic in on-chip architectures, which can be deemed as the solutions to the boundary extremes of a class of utility maximization problem. At one extreme, we consider the so-called Rate-Sum flow control scheme, which aims at improving the performance of the underlying system by roughly maximizing throughput while satisfying capacity constraints. At the other extreme, we deem the Max-Min flow control, whose concern is to maintain Max-Min fairness in rate allocation by fairly sacrificing the throughput. We then elaborate our argument through a weighting mechanism in order to achieve a balance between the orthogonal goals of performance and fairness. Moreover, we investigate the implementation facets of the presented flow control schemes in on-chip architectures. Finally, we validate the proposed flow control schemes and the subsequent arguments through extensive simulation experiments.
AB - We consider two flow control schemes for Best Effort traffic in on-chip architectures, which can be deemed as the solutions to the boundary extremes of a class of utility maximization problem. At one extreme, we consider the so-called Rate-Sum flow control scheme, which aims at improving the performance of the underlying system by roughly maximizing throughput while satisfying capacity constraints. At the other extreme, we deem the Max-Min flow control, whose concern is to maintain Max-Min fairness in rate allocation by fairly sacrificing the throughput. We then elaborate our argument through a weighting mechanism in order to achieve a balance between the orthogonal goals of performance and fairness. Moreover, we investigate the implementation facets of the presented flow control schemes in on-chip architectures. Finally, we validate the proposed flow control schemes and the subsequent arguments through extensive simulation experiments.
UR - http://www.scopus.com/inward/record.url?scp=70449810244&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70449810244&partnerID=8YFLogxK
U2 - 10.1109/IPDPS.2009.5161186
DO - 10.1109/IPDPS.2009.5161186
M3 - Conference contribution
SN - 9781424437504
BT - IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium
ER -