Shortest path routing algorithm for hierarchical interconnection network-on-chip

Omair Inam*, Sharifa Al Khanjari, Wim Vanderbauwhede

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

5 Citations (Scopus)

Abstract

Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k - 1) time where k = logn4 - 2 and k > 0, in worst case to determine the next node along the shortest path.

Original languageEnglish
Pages (from-to)409-414
Number of pages6
JournalProcedia Computer Science
Volume56
Issue number1
DOIs
Publication statusPublished - 2015
Externally publishedYes
Event29th European Conference on Solid-State Transducers, EUROSENSORS 2015; Freiburg; Germany; 6 September 2015 through 9 September 2015. - Freiburg, Germany
Duration: Sep 6 2015Sep 9 2015

Keywords

  • Hierarchical graph representation
  • Hierarchical interconnection network
  • Network-on-chip
  • Shortest path routing algorithm

ASJC Scopus subject areas

  • Computer Science(all)

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