Shortest path routing algorithm for hierarchical interconnection network-on-chip

Omair Inam; Sharifa Al Khanjari; Wim Vanderbauwhede

doi:10.1016/j.procs.2015.07.228

Shortest path routing algorithm for hierarchical interconnection network-on-chip

Omair Inam^*, Sharifa Al Khanjari, Wim Vanderbauwhede

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

5 Citations (Scopus)

Abstract

Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k - 1) time where k = logⁿ₄ - 2 and k > 0, in worst case to determine the next node along the shortest path.

Original language	English
Pages (from-to)	409-414
Number of pages	6
Journal	Procedia Computer Science
Volume	56
Issue number	1
DOIs	https://doi.org/10.1016/j.procs.2015.07.228
Publication status	Published - 2015
Externally published	Yes
Event	29th European Conference on Solid-State Transducers, EUROSENSORS 2015; Freiburg; Germany; 6 September 2015 through 9 September 2015. - Freiburg, Germany Duration: Sept 6 2015 → Sept 9 2015

Keywords

Hierarchical graph representation
Hierarchical interconnection network
Network-on-chip
Shortest path routing algorithm

ASJC Scopus subject areas

Computer Science(all)

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10.1016/j.procs.2015.07.228

Cite this

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title = "Shortest path routing algorithm for hierarchical interconnection network-on-chip",

abstract = "Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k - 1) time where k = logn4 - 2 and k > 0, in worst case to determine the next node along the shortest path.",

keywords = "Hierarchical graph representation, Hierarchical interconnection network, Network-on-chip, Shortest path routing algorithm",

author = "Omair Inam and {Al Khanjari}, Sharifa and Wim Vanderbauwhede",

note = "Publisher Copyright: {\textcopyright} 2015 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license.; 29th European Conference on Solid-State Transducers, EUROSENSORS 2015; Freiburg; Germany; 6 September 2015 through 9 September 2015. ; Conference date: 06-09-2015 Through 09-09-2015",

year = "2015",

doi = "10.1016/j.procs.2015.07.228",

language = "English",

volume = "56",

pages = "409--414",

journal = "Procedia Computer Science",

issn = "1877-0509",

publisher = "Elsevier BV",

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TY - JOUR

T1 - Shortest path routing algorithm for hierarchical interconnection network-on-chip

AU - Inam, Omair

AU - Al Khanjari, Sharifa

AU - Vanderbauwhede, Wim

PY - 2015

Y1 - 2015

N2 - Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k - 1) time where k = logn4 - 2 and k > 0, in worst case to determine the next node along the shortest path.

AB - Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k - 1) time where k = logn4 - 2 and k > 0, in worst case to determine the next node along the shortest path.

KW - Hierarchical graph representation

KW - Hierarchical interconnection network

KW - Network-on-chip

KW - Shortest path routing algorithm

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DO - 10.1016/j.procs.2015.07.228

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AN - SCOPUS:84939131729

SN - 1877-0509

VL - 56

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T2 - 29th European Conference on Solid-State Transducers, EUROSENSORS 2015; Freiburg; Germany; 6 September 2015 through 9 September 2015.

Y2 - 6 September 2015 through 9 September 2015

ER -

Shortest path routing algorithm for hierarchical interconnection network-on-chip

Abstract

Keywords

ASJC Scopus subject areas

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