Selection of polynomials for Cyclic Redundancy Check for the use of high speed embedded - An algorithmic procedure

Cyclic Redundancy Check (CRC) technique which is widely used tools in globally standardized telecommunications systems for dealing with data errors detection and correction have not been fully standardized. Most of the CRCs in current use have some weakness with respect to strength or construction. Standardization of CRCs would allow for better designed CRCs to come into common use is primarily limited due to the complexity of search procedures of the primitive characteristic polynomials. To this direction this paper proposes a method of simplifying the computation and complexity of the search procedure of the primitive characteristic polynomials in order to facilitate implementation of the circuitry for high-speed CRC computation in standard CMOS technology.