Performance modelling of a true fully adaptive routing algorithm

A. Khonsari, H. Sarbazi-Azad, M. Ould-Khaoua

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Several recent studies have revealed that deadlocks occur very infrequently in the network, especially when enough routing freedom is provided. Routing algorithms based on deadlock avoidance reserve some virtual channels or routing options to specifically deal with deadlocks, and as a result they are not utilized most of the time. Routing algorithms based on deadlock recovery allow messages to use all available virtual channels to cross the network, and efficiently handle infrequently occurred deadlocks. This paper describes a new analytical model of a true fully adaptive routing (TFAR) algorithm with software-based deadlock recovery in k-ary n-cubes. Results obtained through simulation experiments confirm that the model predicts message latency with a good degree of accuracy under different working conditions.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages393-400
Number of pages8
Volume2001-January
ISBN (Print)0769512577
DOIs
Publication statusPublished - 2001
EventInternational Conference on Parallel Processing, ICPP 2001 - Valencia, Spain
Duration: Sep 3 2001Sep 7 2001

Other

OtherInternational Conference on Parallel Processing, ICPP 2001
CountrySpain
CityValencia
Period9/3/019/7/01

Keywords

  • Analytical models
  • Bandwidth
  • Computer networks
  • Delay
  • Electronic mail
  • Employee welfare
  • Hardware
  • Predictive models
  • Routing
  • System recovery

ASJC Scopus subject areas

  • Software
  • Mathematics(all)
  • Hardware and Architecture

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  • Cite this

    Khonsari, A., Sarbazi-Azad, H., & Ould-Khaoua, M. (2001). Performance modelling of a true fully adaptive routing algorithm. In Proceedings of the International Conference on Parallel Processing (Vol. 2001-January, pp. 393-400). [952085] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.2001.952085