Performance modelling and analysis of pipelined circuit switching in hypercubes with faults

F. Safaei, A. Khonsari, M. Fathy, M. Ould-Khaoua

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multicomputer systems are more susceptible to failure than conventional uniprocessor machines. This is because as the system size scales up, the probability of a component failure also increases. It is therefore essential to use fault-tolerant routing that allows messages to reach their destinations even in the presence of faults. Pipelined Circuit Switching (PCS) that has been employed as an efficient switching method in the design of fault-tolerant routing algorithm for reliable interprocessor networks can route a message from source to destination, even in the presence of faulty components. The analytical model of PCS for common networks (e.g., hypercube) in the absence of faulty components has recently been reported in the literature. However, none of these analytical models attempt to capture the effects of faulty nodes or links in the performance of the networks. This paper proposes a new analytical model of PCS, in the presence of faulty nodes, in the hypercube networks augmented with virtual channels. The model makes latency predictions that are in good agreement with those obtained from simulation experiments.

Original languageEnglish
Title of host publicationProceedings - Eighth International Conference on High-Performance Computing in Asia-Pacific Region, HPC Asia 2005
Pages265-272
Number of pages8
Volume2005
DOIs
Publication statusPublished - 2005
Event8th International Conference on High-Performance Computing in Asia-Pacific Region, HPC Asia 2005 - Beijing, China
Duration: Nov 30 2005Dec 3 2005

Other

Other8th International Conference on High-Performance Computing in Asia-Pacific Region, HPC Asia 2005
CountryChina
CityBeijing
Period11/30/0512/3/05

Fingerprint

Switching circuits
Hypercube networks
Analytical models
Routing algorithms
Experiments

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Safaei, F., Khonsari, A., Fathy, M., & Ould-Khaoua, M. (2005). Performance modelling and analysis of pipelined circuit switching in hypercubes with faults. In Proceedings - Eighth International Conference on High-Performance Computing in Asia-Pacific Region, HPC Asia 2005 (Vol. 2005, pp. 265-272). [1592278] https://doi.org/10.1109/HPCASIA.2005.77

Performance modelling and analysis of pipelined circuit switching in hypercubes with faults. / Safaei, F.; Khonsari, A.; Fathy, M.; Ould-Khaoua, M.

Proceedings - Eighth International Conference on High-Performance Computing in Asia-Pacific Region, HPC Asia 2005. Vol. 2005 2005. p. 265-272 1592278.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Safaei, F, Khonsari, A, Fathy, M & Ould-Khaoua, M 2005, Performance modelling and analysis of pipelined circuit switching in hypercubes with faults. in Proceedings - Eighth International Conference on High-Performance Computing in Asia-Pacific Region, HPC Asia 2005. vol. 2005, 1592278, pp. 265-272, 8th International Conference on High-Performance Computing in Asia-Pacific Region, HPC Asia 2005, Beijing, China, 11/30/05. https://doi.org/10.1109/HPCASIA.2005.77
Safaei F, Khonsari A, Fathy M, Ould-Khaoua M. Performance modelling and analysis of pipelined circuit switching in hypercubes with faults. In Proceedings - Eighth International Conference on High-Performance Computing in Asia-Pacific Region, HPC Asia 2005. Vol. 2005. 2005. p. 265-272. 1592278 https://doi.org/10.1109/HPCASIA.2005.77
Safaei, F. ; Khonsari, A. ; Fathy, M. ; Ould-Khaoua, M. / Performance modelling and analysis of pipelined circuit switching in hypercubes with faults. Proceedings - Eighth International Conference on High-Performance Computing in Asia-Pacific Region, HPC Asia 2005. Vol. 2005 2005. pp. 265-272
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