Abstract
Circuit Switching (CS) has been suggested as an efficient switching method for supporting simultaneous communications (such as data, voice, and images) across parallel systems due to its ability to preserve both communication performance and fault-tolerant demands in such systems. In this paper we present an efficient scheme to capture the mean message latency in 2-D torus with CS in the presence of faulty components. We have also conducted extensive simulation experiments, the results of which are used to validate the analytical model.
Original language | English |
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Title of host publication | PARELEC 2006 - Proceedings: International Symposium on Parallel Computing in Electrical Engineering |
Pages | 239-244 |
Number of pages | 6 |
DOIs | |
Publication status | Published - 2006 |
Event | International Symposium on Parallel Computing in Electrical Engineering, PARELEC 2006 - Bialystok, Poland Duration: Sep 13 2006 → Sep 17 2006 |
Other
Other | International Symposium on Parallel Computing in Electrical Engineering, PARELEC 2006 |
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Country | Poland |
City | Bialystok |
Period | 9/13/06 → 9/17/06 |
ASJC Scopus subject areas
- Computer Science Applications
- Electrical and Electronic Engineering