Performance modeling of fault-tolerant circuit-switched communication networks

F. Safaei; A. Khonsari; M. Fathy; N. Alzeidi; M. Ould-Khaoua

doi:10.1109/PARELEC.2006.67

Performance modeling of fault-tolerant circuit-switched communication networks

F. Safaei^*, A. Khonsari, M. Fathy, N. Alzeidi, M. Ould-Khaoua

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Circuit Switching (CS) has been suggested as an efficient switching method for supporting simultaneous communications (such as data, voice, and images) across parallel systems due to its ability to preserve both communication performance and fault-tolerant demands in such systems. In this paper we present an efficient scheme to capture the mean message latency in 2-D torus with CS in the presence of faulty components. We have also conducted extensive simulation experiments, the results of which are used to validate the analytical model.

Original language	English
Title of host publication	PARELEC 2006 - Proceedings: International Symposium on Parallel Computing in Electrical Engineering
Pages	239-244
Number of pages	6
DOIs	https://doi.org/10.1109/PARELEC.2006.67
Publication status	Published - 2006
Event	International Symposium on Parallel Computing in Electrical Engineering, PARELEC 2006 - Bialystok, Poland Duration: Sep 13 2006 → Sep 17 2006

Other

Other	International Symposium on Parallel Computing in Electrical Engineering, PARELEC 2006
Country/Territory	Poland
City	Bialystok
Period	9/13/06 → 9/17/06

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

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10.1109/PARELEC.2006.67

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Safaei, F, Khonsari, A, Fathy, M, Alzeidi, N & Ould-Khaoua, M 2006, Performance modeling of fault-tolerant circuit-switched communication networks. in PARELEC 2006 - Proceedings: International Symposium on Parallel Computing in Electrical Engineering., 1698667, pp. 239-244, International Symposium on Parallel Computing in Electrical Engineering, PARELEC 2006, Bialystok, Poland, 9/13/06. https://doi.org/10.1109/PARELEC.2006.67

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author = "F. Safaei and A. Khonsari and M. Fathy and N. Alzeidi and M. Ould-Khaoua",

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doi = "10.1109/PARELEC.2006.67",

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AU - Ould-Khaoua, M.

PY - 2006

Y1 - 2006

N2 - Circuit Switching (CS) has been suggested as an efficient switching method for supporting simultaneous communications (such as data, voice, and images) across parallel systems due to its ability to preserve both communication performance and fault-tolerant demands in such systems. In this paper we present an efficient scheme to capture the mean message latency in 2-D torus with CS in the presence of faulty components. We have also conducted extensive simulation experiments, the results of which are used to validate the analytical model.

AB - Circuit Switching (CS) has been suggested as an efficient switching method for supporting simultaneous communications (such as data, voice, and images) across parallel systems due to its ability to preserve both communication performance and fault-tolerant demands in such systems. In this paper we present an efficient scheme to capture the mean message latency in 2-D torus with CS in the presence of faulty components. We have also conducted extensive simulation experiments, the results of which are used to validate the analytical model.

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BT - PARELEC 2006 - Proceedings: International Symposium on Parallel Computing in Electrical Engineering

T2 - International Symposium on Parallel Computing in Electrical Engineering, PARELEC 2006

Y2 - 13 September 2006 through 17 September 2006

ER -

Performance modeling of fault-tolerant circuit-switched communication networks

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