On Reducing Power during Test Process of FPGAs

The Field Programmable Gate Arrays (FPGAs) market is forecasted to reach capitalization of 25.85 billion USD by 2030 as it grows currently at a compound annual growth rate of 11.2%. FPGAs market however, destined to be highly competitive given a variety of intrinsic factors such as economics of scale, the kinds of items and products available and the downright favorable conditions for the bigger firms that have much lower fixed costs. In a wide range of industries, which comprises automotive, top end level computing, defense, consumer electronics and communications is bound to be interesting. The sheer demand for FPGAs use in Internet of Things (IoT) devices, even branches of Artificial Intelligence (AI) that deal with giving computers the ability to understand text and spoken words very much the same way as humans do, based infotainment, and wide range of systems combining innovative technologies; both in terms of hardware (IoT and software). The R&D sector of FPGA market is very well funded and therefore innovation in the FPGA sector has been implemented at breath taking speeds. Power consumption is the greatest issue facing FPGAs especially during testing process, and this is the main topic research community in field of FPGAs concentrates on. FPGAs unlock advantages for Deep Learning (DL) and AI based solutions, which comprises higher performance with low latency and high throughput. Although, FPGAs being highly attributed are associated with the weakness of their power consumption and that issue cannot be ignored. Hence, power reduction has been an important research area, considered by the research community working in the field of FPGAs. The issue of power consumption is more of concern during the testing process of FPGAs. This talk is designed to look into the different mechanisms of reducing the power consumption during the test process of FPGAs.