On quantifying fault patterns of the mesh interconnect networks

F. Safaei, M. Fathy, A. Khonsari, M. Ould-Khaoua, H. Shafiei, S. Khosravipour

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

One of the key issues in the design of Multiprocessors System-on-Chip (MP-SoCs), multicomputers, and peer-to-peer networks is the development of an efficient communication network to provide high throughput and low latency and its ability to survive beyond the failure of individual components. Generally, the faulty components may be coalesced into fault regions, which are classified into convex and concave shapes. In this paper, we propose a mathematical solution for counting the number of common fault patterns in a 2-D mesh interconnect network including both convex (I-shape, II-shape, □-shape) and concave (L-shape, U-shape, T-shape, +-shape, H-shape) regions. The results presented in this paper which have been validated through simulation experiments can play a key role when studying, particularly, the performance analysis of fault-tolerant routing algorithms and measure of a network fault-tolerance expressed as the probability of a disconnection.

Original languageEnglish
Title of host publicationProceedings - International Conference on Advanced Information Networking and Applications, AINA
Pages956-961
Number of pages6
DOIs
Publication statusPublished - 2007
Event21st International Conference on Advanced Information Networking and Applications, AINA 2007 - Niagara Falls, ON, Canada
Duration: May 21 2007May 23 2007

Other

Other21st International Conference on Advanced Information Networking and Applications, AINA 2007
CountryCanada
CityNiagara Falls, ON
Period5/21/075/23/07

Fingerprint

Peer to peer networks
Routing algorithms
Fault tolerance
Telecommunication networks
Throughput
Experiments
System-on-chip

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Safaei, F., Fathy, M., Khonsari, A., Ould-Khaoua, M., Shafiei, H., & Khosravipour, S. (2007). On quantifying fault patterns of the mesh interconnect networks. In Proceedings - International Conference on Advanced Information Networking and Applications, AINA (pp. 956-961). [4220994] https://doi.org/10.1109/AINA.2007.98

On quantifying fault patterns of the mesh interconnect networks. / Safaei, F.; Fathy, M.; Khonsari, A.; Ould-Khaoua, M.; Shafiei, H.; Khosravipour, S.

Proceedings - International Conference on Advanced Information Networking and Applications, AINA. 2007. p. 956-961 4220994.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Safaei, F, Fathy, M, Khonsari, A, Ould-Khaoua, M, Shafiei, H & Khosravipour, S 2007, On quantifying fault patterns of the mesh interconnect networks. in Proceedings - International Conference on Advanced Information Networking and Applications, AINA., 4220994, pp. 956-961, 21st International Conference on Advanced Information Networking and Applications, AINA 2007, Niagara Falls, ON, Canada, 5/21/07. https://doi.org/10.1109/AINA.2007.98
Safaei F, Fathy M, Khonsari A, Ould-Khaoua M, Shafiei H, Khosravipour S. On quantifying fault patterns of the mesh interconnect networks. In Proceedings - International Conference on Advanced Information Networking and Applications, AINA. 2007. p. 956-961. 4220994 https://doi.org/10.1109/AINA.2007.98
Safaei, F. ; Fathy, M. ; Khonsari, A. ; Ould-Khaoua, M. ; Shafiei, H. ; Khosravipour, S. / On quantifying fault patterns of the mesh interconnect networks. Proceedings - International Conference on Advanced Information Networking and Applications, AINA. 2007. pp. 956-961
@inproceedings{23e95c956b8e444f9e7ee43bdb392d7c,
title = "On quantifying fault patterns of the mesh interconnect networks",
abstract = "One of the key issues in the design of Multiprocessors System-on-Chip (MP-SoCs), multicomputers, and peer-to-peer networks is the development of an efficient communication network to provide high throughput and low latency and its ability to survive beyond the failure of individual components. Generally, the faulty components may be coalesced into fault regions, which are classified into convex and concave shapes. In this paper, we propose a mathematical solution for counting the number of common fault patterns in a 2-D mesh interconnect network including both convex (I-shape, II-shape, □-shape) and concave (L-shape, U-shape, T-shape, +-shape, H-shape) regions. The results presented in this paper which have been validated through simulation experiments can play a key role when studying, particularly, the performance analysis of fault-tolerant routing algorithms and measure of a network fault-tolerance expressed as the probability of a disconnection.",
author = "F. Safaei and M. Fathy and A. Khonsari and M. Ould-Khaoua and H. Shafiei and S. Khosravipour",
year = "2007",
doi = "10.1109/AINA.2007.98",
language = "English",
isbn = "0769528465",
pages = "956--961",
booktitle = "Proceedings - International Conference on Advanced Information Networking and Applications, AINA",

}

TY - GEN

T1 - On quantifying fault patterns of the mesh interconnect networks

AU - Safaei, F.

AU - Fathy, M.

AU - Khonsari, A.

AU - Ould-Khaoua, M.

AU - Shafiei, H.

AU - Khosravipour, S.

PY - 2007

Y1 - 2007

N2 - One of the key issues in the design of Multiprocessors System-on-Chip (MP-SoCs), multicomputers, and peer-to-peer networks is the development of an efficient communication network to provide high throughput and low latency and its ability to survive beyond the failure of individual components. Generally, the faulty components may be coalesced into fault regions, which are classified into convex and concave shapes. In this paper, we propose a mathematical solution for counting the number of common fault patterns in a 2-D mesh interconnect network including both convex (I-shape, II-shape, □-shape) and concave (L-shape, U-shape, T-shape, +-shape, H-shape) regions. The results presented in this paper which have been validated through simulation experiments can play a key role when studying, particularly, the performance analysis of fault-tolerant routing algorithms and measure of a network fault-tolerance expressed as the probability of a disconnection.

AB - One of the key issues in the design of Multiprocessors System-on-Chip (MP-SoCs), multicomputers, and peer-to-peer networks is the development of an efficient communication network to provide high throughput and low latency and its ability to survive beyond the failure of individual components. Generally, the faulty components may be coalesced into fault regions, which are classified into convex and concave shapes. In this paper, we propose a mathematical solution for counting the number of common fault patterns in a 2-D mesh interconnect network including both convex (I-shape, II-shape, □-shape) and concave (L-shape, U-shape, T-shape, +-shape, H-shape) regions. The results presented in this paper which have been validated through simulation experiments can play a key role when studying, particularly, the performance analysis of fault-tolerant routing algorithms and measure of a network fault-tolerance expressed as the probability of a disconnection.

UR - http://www.scopus.com/inward/record.url?scp=34548805418&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34548805418&partnerID=8YFLogxK

U2 - 10.1109/AINA.2007.98

DO - 10.1109/AINA.2007.98

M3 - Conference contribution

SN - 0769528465

SN - 9780769528465

SP - 956

EP - 961

BT - Proceedings - International Conference on Advanced Information Networking and Applications, AINA

ER -