On quantifying fault patterns of the mesh interconnect networks

F. Safaei*, M. Fathy, A. Khonsari, M. Ould-Khaoua, H. Shafiei, S. Khosravipour

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

One of the key issues in the design of Multiprocessors System-on-Chip (MP-SoCs), multicomputers, and peer-to-peer networks is the development of an efficient communication network to provide high throughput and low latency and its ability to survive beyond the failure of individual components. Generally, the faulty components may be coalesced into fault regions, which are classified into convex and concave shapes. In this paper, we propose a mathematical solution for counting the number of common fault patterns in a 2-D mesh interconnect network including both convex (I-shape, II-shape, □-shape) and concave (L-shape, U-shape, T-shape, +-shape, H-shape) regions. The results presented in this paper which have been validated through simulation experiments can play a key role when studying, particularly, the performance analysis of fault-tolerant routing algorithms and measure of a network fault-tolerance expressed as the probability of a disconnection.

Original languageEnglish
Title of host publicationProceedings - 21st International Conference on Advanced Information Networking and Applications, AINA 2007
Pages956-961
Number of pages6
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event21st International Conference on Advanced Information Networking and Applications, AINA 2007 - Niagara Falls, ON, Canada
Duration: May 21 2007May 23 2007

Publication series

NameProceedings - International Conference on Advanced Information Networking and Applications, AINA
ISSN (Print)1550-445X

Other

Other21st International Conference on Advanced Information Networking and Applications, AINA 2007
Country/TerritoryCanada
CityNiagara Falls, ON
Period5/21/075/23/07

ASJC Scopus subject areas

  • General Engineering

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