M8NoC: An 8-degree mesh-based NoC architecture

N. Alzeidi; K. Day; A. Touzene; B. Arafeh

doi:10.1109/ICUFN.2012.6261691

M8NoC: An 8-degree mesh-based NoC architecture

N. Alzeidi^*, K. Day, A. Touzene, B. Arafeh

^*Corresponding author for this work

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In multicore systems, low transmission delay and high throughput are essential to fully harness the computational power offered by tens or hundreds of cores. In this paper we present a new NoC architecture (M8NoC) by devising changes to the topology and routing of the simple mesh network. The changes allow overcoming some limitations of the mesh network by decreasing the diameter, decreasing the average distance and increasing the bisection width. Preliminary analytical investigation have shown potential enhancements in performance and reliability. Namely, the M8NoC achieves higher throughput and lower latency compared to its mesh, torus and spidergon counterparts.

Original language	English
Title of host publication	ICUFN 2012 - 4th International Conference on Ubiquitous and Future Networks, Final Program
Pages	192-197
Number of pages	6
DOIs	https://doi.org/10.1109/ICUFN.2012.6261691
Publication status	Published - 2012
Event	4th International Conference on Ubiquitous and Future Networks, ICUFN 2012 - Phuket, Thailand Duration: Jul 4 2012 → Jul 6 2012

Other

Other	4th International Conference on Ubiquitous and Future Networks, ICUFN 2012
Country/Territory	Thailand
City	Phuket
Period	7/4/12 → 7/6/12

Keywords

multicore systems
Network-on-Chip
performance evaluation
routing
topology
wormhole switching

ASJC Scopus subject areas

Computer Networks and Communications

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10.1109/ICUFN.2012.6261691

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@inproceedings{f60c3d091a844c289417474f81d78f44,

title = "M8NoC: An 8-degree mesh-based NoC architecture",

abstract = "In multicore systems, low transmission delay and high throughput are essential to fully harness the computational power offered by tens or hundreds of cores. In this paper we present a new NoC architecture (M8NoC) by devising changes to the topology and routing of the simple mesh network. The changes allow overcoming some limitations of the mesh network by decreasing the diameter, decreasing the average distance and increasing the bisection width. Preliminary analytical investigation have shown potential enhancements in performance and reliability. Namely, the M8NoC achieves higher throughput and lower latency compared to its mesh, torus and spidergon counterparts.",

keywords = "multicore systems, Network-on-Chip, performance evaluation, routing, topology, wormhole switching",

author = "N. Alzeidi and K. Day and A. Touzene and B. Arafeh",

year = "2012",

doi = "10.1109/ICUFN.2012.6261691",

language = "English",

isbn = "9781467313773",

pages = "192--197",

booktitle = "ICUFN 2012 - 4th International Conference on Ubiquitous and Future Networks, Final Program",

note = "4th International Conference on Ubiquitous and Future Networks, ICUFN 2012 ; Conference date: 04-07-2012 Through 06-07-2012",

}

TY - GEN

T1 - M8NoC

T2 - 4th International Conference on Ubiquitous and Future Networks, ICUFN 2012

AU - Alzeidi, N.

AU - Day, K.

AU - Touzene, A.

AU - Arafeh, B.

PY - 2012

Y1 - 2012

N2 - In multicore systems, low transmission delay and high throughput are essential to fully harness the computational power offered by tens or hundreds of cores. In this paper we present a new NoC architecture (M8NoC) by devising changes to the topology and routing of the simple mesh network. The changes allow overcoming some limitations of the mesh network by decreasing the diameter, decreasing the average distance and increasing the bisection width. Preliminary analytical investigation have shown potential enhancements in performance and reliability. Namely, the M8NoC achieves higher throughput and lower latency compared to its mesh, torus and spidergon counterparts.

AB - In multicore systems, low transmission delay and high throughput are essential to fully harness the computational power offered by tens or hundreds of cores. In this paper we present a new NoC architecture (M8NoC) by devising changes to the topology and routing of the simple mesh network. The changes allow overcoming some limitations of the mesh network by decreasing the diameter, decreasing the average distance and increasing the bisection width. Preliminary analytical investigation have shown potential enhancements in performance and reliability. Namely, the M8NoC achieves higher throughput and lower latency compared to its mesh, torus and spidergon counterparts.

KW - multicore systems

KW - Network-on-Chip

KW - performance evaluation

KW - routing

KW - topology

KW - wormhole switching

UR - http://www.scopus.com/inward/record.url?scp=84866422716&partnerID=8YFLogxK

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U2 - 10.1109/ICUFN.2012.6261691

DO - 10.1109/ICUFN.2012.6261691

M3 - Conference contribution

AN - SCOPUS:84866422716

SN - 9781467313773

SP - 192

EP - 197

BT - ICUFN 2012 - 4th International Conference on Ubiquitous and Future Networks, Final Program

Y2 - 4 July 2012 through 6 July 2012

ER -

M8NoC: An 8-degree mesh-based NoC architecture

Abstract

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Keywords

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