Impact of leaky bucket regulation on the performance of combined I/O buffering in ATM switches

Adel Ben Mnaouer, Khaled Day, Khalil Shihab

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We propose a Colored Petri Net (CPN) model used for prototyping and modeling a complex switching scheme for ATM switches based on the combined I/O buffering technique. The new scheme that was proposed recently in the literature is evaluated here within an overall setting that includes the traffic regulations enforced by the leaky bucket algorithm. The new scheme is based on splitting the traffic coming into input lines into two priority queues (High and Low) where traffic destined to busy ports is directed to the low priority queue. This scheme was compared against pure combined I/O buffering and simulation results showed that the new scheme pays back in decreasing transmission delay only when the traffic increases beyond a certain level. In addition the sensitivity analysis of the bucket size showed also that this latter affects the performance of the system only at high loads.

Original languageEnglish
Title of host publicationProceedings of the IEEE International Conference on Systems, Man and Cybernetics
EditorsA. El Kamel, K. Mellouli, P. Borne
Pages504-509
Number of pages6
Volume1
Publication statusPublished - 2002
Event2002 IEEE International Conference on Systems, Man and Cybernetics - Yasmine Hammamet, Tunisia
Duration: Oct 6 2002Oct 9 2002

Other

Other2002 IEEE International Conference on Systems, Man and Cybernetics
CountryTunisia
CityYasmine Hammamet
Period10/6/0210/9/02

Fingerprint

Automatic teller machines
Petri nets
Sensitivity analysis
Switches

Keywords

  • ATM Switches
  • Combined I/O Buffering
  • Leaky Bucket regulator
  • Priority Queues

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Mnaouer, A. B., Day, K., & Shihab, K. (2002). Impact of leaky bucket regulation on the performance of combined I/O buffering in ATM switches. In A. El Kamel, K. Mellouli, & P. Borne (Eds.), Proceedings of the IEEE International Conference on Systems, Man and Cybernetics (Vol. 1, pp. 504-509)

Impact of leaky bucket regulation on the performance of combined I/O buffering in ATM switches. / Mnaouer, Adel Ben; Day, Khaled; Shihab, Khalil.

Proceedings of the IEEE International Conference on Systems, Man and Cybernetics. ed. / A. El Kamel; K. Mellouli; P. Borne. Vol. 1 2002. p. 504-509.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mnaouer, AB, Day, K & Shihab, K 2002, Impact of leaky bucket regulation on the performance of combined I/O buffering in ATM switches. in A El Kamel, K Mellouli & P Borne (eds), Proceedings of the IEEE International Conference on Systems, Man and Cybernetics. vol. 1, pp. 504-509, 2002 IEEE International Conference on Systems, Man and Cybernetics, Yasmine Hammamet, Tunisia, 10/6/02.
Mnaouer AB, Day K, Shihab K. Impact of leaky bucket regulation on the performance of combined I/O buffering in ATM switches. In El Kamel A, Mellouli K, Borne P, editors, Proceedings of the IEEE International Conference on Systems, Man and Cybernetics. Vol. 1. 2002. p. 504-509
Mnaouer, Adel Ben ; Day, Khaled ; Shihab, Khalil. / Impact of leaky bucket regulation on the performance of combined I/O buffering in ATM switches. Proceedings of the IEEE International Conference on Systems, Man and Cybernetics. editor / A. El Kamel ; K. Mellouli ; P. Borne. Vol. 1 2002. pp. 504-509
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