Abstract
In this paper, we present an efficient hardware/software (HW/SW) implementation of the Vector Median Filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using μClinux as operating system.. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007 |
| Pages | 101-104 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2007 |
| Event | 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007 - Bordeaux, France Duration: Jul 2 2007 → Jul 5 2007 |
Other
| Other | 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007 |
|---|---|
| Country | France |
| City | Bordeaux |
| Period | 7/2/07 → 7/5/07 |
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Keywords
- Embedded system
- FPGA
- NIOS II softcore processor
- SoPC
- VMF
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
HW/SW FPGA implementation of vector median filter. / Boudabous, A.; Ben Atitallah, A.; Kadionik, P.; Khriji, L.; Masmoudi, N.
Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007. 2007. p. 101-104 4401821.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - HW/SW FPGA implementation of vector median filter
AU - Boudabous, A.
AU - Ben Atitallah, A.
AU - Kadionik, P.
AU - Khriji, L.
AU - Masmoudi, N.
PY - 2007
Y1 - 2007
N2 - In this paper, we present an efficient hardware/software (HW/SW) implementation of the Vector Median Filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using μClinux as operating system.. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.
AB - In this paper, we present an efficient hardware/software (HW/SW) implementation of the Vector Median Filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using μClinux as operating system.. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.
KW - Embedded system
KW - FPGA
KW - NIOS II softcore processor
KW - SoPC
KW - VMF
UR - http://www.scopus.com/inward/record.url?scp=47349105527&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=47349105527&partnerID=8YFLogxK
U2 - 10.1109/RME.2007.4401821
DO - 10.1109/RME.2007.4401821
M3 - Conference contribution
AN - SCOPUS:47349105527
SN - 1424410002
SN - 9781424410002
SP - 101
EP - 104
BT - Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007
ER -