HW/SW FPGA implementation of vector median filter

A. Boudabous, A. Ben Atitallah, P. Kadionik, L. Khriji, N. Masmoudi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we present an efficient hardware/software (HW/SW) implementation of the Vector Median Filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using μClinux as operating system.. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.

Original languageEnglish
Title of host publicationProceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007
Pages101-104
Number of pages4
DOIs
Publication statusPublished - 2007
Event2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007 - Bordeaux, France
Duration: Jul 2 2007Jul 5 2007

Other

Other2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007
CountryFrance
CityBordeaux
Period7/2/077/5/07

Keywords

  • Embedded system
  • FPGA
  • NIOS II softcore processor
  • SoPC
  • VMF

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Boudabous, A., Ben Atitallah, A., Kadionik, P., Khriji, L., & Masmoudi, N. (2007). HW/SW FPGA implementation of vector median filter. In Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007 (pp. 101-104). [4401821] https://doi.org/10.1109/RME.2007.4401821