HW/SW FPGA implementation of vector median filter

A. Boudabous; A. Ben Atitallah; P. Kadionik; L. Khriji; N. Masmoudi

doi:10.1109/RME.2007.4401821

HW/SW FPGA implementation of vector median filter

A. Boudabous^*, A. Ben Atitallah, P. Kadionik, L. Khriji, N. Masmoudi

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this paper, we present an efficient hardware/software (HW/SW) implementation of the Vector Median Filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using μClinux as operating system.. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.

Original language	English
Title of host publication	Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007
Pages	101-104
Number of pages	4
DOIs	https://doi.org/10.1109/RME.2007.4401821
Publication status	Published - 2007
Event	2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007 - Bordeaux, France Duration: Jul 2 2007 → Jul 5 2007

Publication series

Name	Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007

Other

Other	2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007
Country/Territory	France
City	Bordeaux
Period	7/2/07 → 7/5/07

Keywords

Embedded system
FPGA
NIOS II softcore processor
SoPC
VMF

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/RME.2007.4401821

Cite this

Boudabous, A., Ben Atitallah, A., Kadionik, P., Khriji, L., & Masmoudi, N. (2007). HW/SW FPGA implementation of vector median filter. In Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007 (pp. 101-104). [4401821] (Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007). https://doi.org/10.1109/RME.2007.4401821

HW/SW FPGA implementation of vector median filter. / Boudabous, A.; Ben Atitallah, A.; Kadionik, P. et al.

Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007. 2007. p. 101-104 4401821 (Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Boudabous, A, Ben Atitallah, A, Kadionik, P, Khriji, L & Masmoudi, N 2007, HW/SW FPGA implementation of vector median filter. in Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007., 4401821, Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007, pp. 101-104, 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007, Bordeaux, France, 7/2/07. https://doi.org/10.1109/RME.2007.4401821

Boudabous A, Ben Atitallah A, Kadionik P, Khriji L, Masmoudi N. HW/SW FPGA implementation of vector median filter. In Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007. 2007. p. 101-104. 4401821. (Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007). doi: 10.1109/RME.2007.4401821

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title = "HW/SW FPGA implementation of vector median filter",

abstract = "In this paper, we present an efficient hardware/software (HW/SW) implementation of the Vector Median Filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using μClinux as operating system.. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.",

keywords = "Embedded system, FPGA, NIOS II softcore processor, SoPC, VMF",

author = "A. Boudabous and {Ben Atitallah}, A. and P. Kadionik and L. Khriji and N. Masmoudi",

year = "2007",

doi = "10.1109/RME.2007.4401821",

language = "English",

isbn = "1424410002",

series = "Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007",

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booktitle = "Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007",

note = "2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007 ; Conference date: 02-07-2007 Through 05-07-2007",

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TY - GEN

T1 - HW/SW FPGA implementation of vector median filter

AU - Boudabous, A.

AU - Ben Atitallah, A.

AU - Kadionik, P.

AU - Khriji, L.

AU - Masmoudi, N.

PY - 2007

Y1 - 2007

N2 - In this paper, we present an efficient hardware/software (HW/SW) implementation of the Vector Median Filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using μClinux as operating system.. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.

AB - In this paper, we present an efficient hardware/software (HW/SW) implementation of the Vector Median Filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using μClinux as operating system.. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.

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KW - FPGA

KW - NIOS II softcore processor

KW - SoPC

KW - VMF

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SN - 1424410002

SN - 9781424410002

T3 - Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007

SP - 101

EP - 104

BT - Proceedings of the 2007 Ph.D Research in Microelectronics and Electronics conference, PRIME 2007

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Y2 - 2 July 2007 through 5 July 2007

ER -

HW/SW FPGA implementation of vector median filter

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