TY - GEN
T1 - HW/SW Co-'esign for Dates Classification on Xilinx Zynq SoC
AU - Ammari, Ahmed Chiheb
AU - Khriji, Lazhar
AU - Awadalla, Medhat
N1 - Funding Information:
This project was funded partially by OMANTEL under grant number “EG/SQU-OT/18/01”, and partially by Sultan Qaboos University (SQU), Deanship of Scientific Research (DSR), under grant number “IG/ENG/ECED/19/01”. The authors, therefore, acknowledge OMANTEL and SQU for their financial support.
Publisher Copyright:
© 2020 FRUCT.
PY - 2020/4
Y1 - 2020/4
N2 - This paper proposes HW/SW Co-design of an automatic classification system of Khalas, Khunaizi, Fardh, Qash, Naghal, and Maan dates fruit varieties in Oman. The system implements pre-processing, segmentation of the colored input images, color and shape-size features extraction followed by ANN-tansig classification. The performance of the proposed system is experimented and 97.26% highest classification accuracy are achieved. The proposed system is prototyped using a selected Zynq 7020 SoC platform featuring, on the same chip, a dual-core ARM Cortex A9 processing System (PS) interconnected with FPGA logic (PL) though high-throughput communication channels. The original classification algorithm is profiled and then a HW/SW Co-design is developed achieving 10.9 fps real time classification performance. This performance is acceptable and represents almost 14 times speedup acceleration comparatively to the original program implementation.
AB - This paper proposes HW/SW Co-design of an automatic classification system of Khalas, Khunaizi, Fardh, Qash, Naghal, and Maan dates fruit varieties in Oman. The system implements pre-processing, segmentation of the colored input images, color and shape-size features extraction followed by ANN-tansig classification. The performance of the proposed system is experimented and 97.26% highest classification accuracy are achieved. The proposed system is prototyped using a selected Zynq 7020 SoC platform featuring, on the same chip, a dual-core ARM Cortex A9 processing System (PS) interconnected with FPGA logic (PL) though high-throughput communication channels. The original classification algorithm is profiled and then a HW/SW Co-design is developed achieving 10.9 fps real time classification performance. This performance is acceptable and represents almost 14 times speedup acceleration comparatively to the original program implementation.
UR - http://www.scopus.com/inward/record.url?scp=85085017143&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85085017143&partnerID=8YFLogxK
U2 - 10.23919/FRUCT48808.2020.9087548
DO - 10.23919/FRUCT48808.2020.9087548
M3 - Conference contribution
AN - SCOPUS:85085017143
T3 - Conference of Open Innovation Association, FRUCT
SP - 10
EP - 15
BT - Proceedings of the 26th Conference of Open Innovations Association FRUCT, FRUCT 2020
A2 - Balandin, Sergey
A2 - Paramonov, Ilya
A2 - Tyutina, Tatiana
PB - IEEE Computer Society
T2 - 26th Conference of Open Innovations Association FRUCT, FRUCT 2020
Y2 - 23 April 2020 through 24 April 2020
ER -