Hardware implementation and experiment validation of the VDDRHF color image filter

A. Boudabous, A. Ben Atitallah, L. Khriji, P. Kadionik, N. Masmoudi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a novel FPGA implementation of Vector Directional Distance Rational Hybrid Filter) (VDDRHF) for mixed noise suppression and fine-details preservation in color images. The Implementation was done, based on FPGA HW/SW validation using efficient hardware optimizations and non linear function approximations. The validation using FPGA board confirms the color image quality preservation. Our proposed architecture proves that HW/SW co-design present a high timing performance compared to software based solutions.

Original languageEnglish
Title of host publication2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10
DOIs
Publication statusPublished - 2010
Event2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10 - Amman, Jordan
Duration: Jun 27 2010 → Jun 29 2010

Other

Other2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10
CountryJordan
CityAmman
Period6/27/10 → 6/29/10

Fingerprint

Field programmable gate arrays (FPGA)
Color
Hardware
Experiments
Image quality

Keywords

  • Architecture
  • Color image
  • FPGA implementation
  • Nios-II
  • Validation
  • VDDRHF filter

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Signal Processing
  • Control and Systems Engineering

Cite this

Boudabous, A., Ben Atitallah, A., Khriji, L., Kadionik, P., & Masmoudi, N. (2010). Hardware implementation and experiment validation of the VDDRHF color image filter. In 2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10 [5585526] https://doi.org/10.1109/SSD.2010.5585526

Hardware implementation and experiment validation of the VDDRHF color image filter. / Boudabous, A.; Ben Atitallah, A.; Khriji, L.; Kadionik, P.; Masmoudi, N.

2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10. 2010. 5585526.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Boudabous, A, Ben Atitallah, A, Khriji, L, Kadionik, P & Masmoudi, N 2010, Hardware implementation and experiment validation of the VDDRHF color image filter. in 2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10., 5585526, 2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10, Amman, Jordan, 6/27/10. https://doi.org/10.1109/SSD.2010.5585526
Boudabous A, Ben Atitallah A, Khriji L, Kadionik P, Masmoudi N. Hardware implementation and experiment validation of the VDDRHF color image filter. In 2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10. 2010. 5585526 https://doi.org/10.1109/SSD.2010.5585526
Boudabous, A. ; Ben Atitallah, A. ; Khriji, L. ; Kadionik, P. ; Masmoudi, N. / Hardware implementation and experiment validation of the VDDRHF color image filter. 2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10. 2010.
@inproceedings{66d85eaf07624dfca3637bc8d36a9577,
title = "Hardware implementation and experiment validation of the VDDRHF color image filter",
abstract = "This paper proposes a novel FPGA implementation of Vector Directional Distance Rational Hybrid Filter) (VDDRHF) for mixed noise suppression and fine-details preservation in color images. The Implementation was done, based on FPGA HW/SW validation using efficient hardware optimizations and non linear function approximations. The validation using FPGA board confirms the color image quality preservation. Our proposed architecture proves that HW/SW co-design present a high timing performance compared to software based solutions.",
keywords = "Architecture, Color image, FPGA implementation, Nios-II, Validation, VDDRHF filter",
author = "A. Boudabous and {Ben Atitallah}, A. and L. Khriji and P. Kadionik and N. Masmoudi",
year = "2010",
doi = "10.1109/SSD.2010.5585526",
language = "English",
isbn = "9781424475346",
booktitle = "2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10",

}

TY - GEN

T1 - Hardware implementation and experiment validation of the VDDRHF color image filter

AU - Boudabous, A.

AU - Ben Atitallah, A.

AU - Khriji, L.

AU - Kadionik, P.

AU - Masmoudi, N.

PY - 2010

Y1 - 2010

N2 - This paper proposes a novel FPGA implementation of Vector Directional Distance Rational Hybrid Filter) (VDDRHF) for mixed noise suppression and fine-details preservation in color images. The Implementation was done, based on FPGA HW/SW validation using efficient hardware optimizations and non linear function approximations. The validation using FPGA board confirms the color image quality preservation. Our proposed architecture proves that HW/SW co-design present a high timing performance compared to software based solutions.

AB - This paper proposes a novel FPGA implementation of Vector Directional Distance Rational Hybrid Filter) (VDDRHF) for mixed noise suppression and fine-details preservation in color images. The Implementation was done, based on FPGA HW/SW validation using efficient hardware optimizations and non linear function approximations. The validation using FPGA board confirms the color image quality preservation. Our proposed architecture proves that HW/SW co-design present a high timing performance compared to software based solutions.

KW - Architecture

KW - Color image

KW - FPGA implementation

KW - Nios-II

KW - Validation

KW - VDDRHF filter

UR - http://www.scopus.com/inward/record.url?scp=78149237291&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78149237291&partnerID=8YFLogxK

U2 - 10.1109/SSD.2010.5585526

DO - 10.1109/SSD.2010.5585526

M3 - Conference contribution

SN - 9781424475346

BT - 2010 7th International Multi-Conference on Systems, Signals and Devices, SSD-10

ER -

Access to Document