FPGA implementation of vector directional distance filter based on HW/SW environment validation

Anis Boudabous, Ahmed Ben Atitallah, Lazhar Khriji, Patrice Kadionik, Nouri Masmoudi

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

In this paper a new FPGA implementation approach of vector directional distance filter (VDDF) using HW/SW solution is presented. The challenges of our solution include ease of implementation, good accuracy and relatively high speed. We use approximations to solve hardware limitations. HW/SW solution uses Nios-II FPGA development board. Experimental results using a number of color images show that the approximated VDDF achieves an excellent balance between computational speed and filtering quality. Moreover, the efficient design processes at 110 MHz system clock and gives a good execution time compared to the software based solution.

Original languageEnglish
Pages (from-to)250-257
Number of pages8
JournalAEU - International Journal of Electronics and Communications
Volume65
Issue number3
DOIs
Publication statusPublished - Mar 2011

Fingerprint

Field programmable gate arrays (FPGA)
Clocks
Color
Hardware

Keywords

  • Color image
  • FPGA implementation
  • Hardware acceleration
  • Nonlinear filter

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

FPGA implementation of vector directional distance filter based on HW/SW environment validation. / Boudabous, Anis; Ben Atitallah, Ahmed; Khriji, Lazhar; Kadionik, Patrice; Masmoudi, Nouri.

In: AEU - International Journal of Electronics and Communications, Vol. 65, No. 3, 03.2011, p. 250-257.

Research output: Contribution to journalArticle

Boudabous, Anis ; Ben Atitallah, Ahmed ; Khriji, Lazhar ; Kadionik, Patrice ; Masmoudi, Nouri. / FPGA implementation of vector directional distance filter based on HW/SW environment validation. In: AEU - International Journal of Electronics and Communications. 2011 ; Vol. 65, No. 3. pp. 250-257.
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