FPGA codesign implementation of vector directional filter

A. Boudabous, A. Ben Atitallah, P. Kadionik, L. Khriji, N. Masmoudi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Recently, Vector Directional Filter (VDF) have been developed either as software based applications or hardware using DSP (digital single processing) technologies. In this paper, we present a new efficient hardware/software (HW/SW) codesign implementation of the VDF using embedded system development board. By means of VHDL language, hardware accelerator including VDF algorithm is implemented with fast pipelined architecture. The remaining parts were realized in software using NIOS II softcore processor and Clinux as operating system. Experimental results confirm that the use of hardware accelerator gives good results concerning image quality and filtering speed.

Original languageEnglish
Title of host publication2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008
DOIs
Publication statusPublished - 2008
Event2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008 - Sousse, Tunisia
Duration: Nov 23 2008Nov 26 2008

Other

Other2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008
CountryTunisia
CitySousse
Period11/23/0811/26/08

Keywords

  • Color image
  • Embedded system
  • FPGA implementation
  • NIOS II
  • VDF

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition
  • Software

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    Boudabous, A., Ben Atitallah, A., Kadionik, P., Khriji, L., & Masmoudi, N. (2008). FPGA codesign implementation of vector directional filter. In 2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008 [4743773] https://doi.org/10.1109/IPTA.2008.4743773