FPGA codesign implementation of vector directional filter

A. Boudabous, A. Ben Atitallah, P. Kadionik, L. Khriji, N. Masmoudi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Recently, Vector Directional Filter (VDF) have been developed either as software based applications or hardware using DSP (digital single processing) technologies. In this paper, we present a new efficient hardware/software (HW/SW) codesign implementation of the VDF using embedded system development board. By means of VHDL language, hardware accelerator including VDF algorithm is implemented with fast pipelined architecture. The remaining parts were realized in software using NIOS II softcore processor and Clinux as operating system. Experimental results confirm that the use of hardware accelerator gives good results concerning image quality and filtering speed.

Original languageEnglish
Title of host publication2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008
DOIs
Publication statusPublished - 2008
Event2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008 - Sousse, Tunisia
Duration: Nov 23 2008Nov 26 2008

Other

Other2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008
CountryTunisia
CitySousse
Period11/23/0811/26/08

Fingerprint

Field programmable gate arrays (FPGA)
Hardware
Particle accelerators
Computer hardware description languages
Embedded systems
Image quality
Processing
Hardware-software codesign

Keywords

  • Color image
  • Embedded system
  • FPGA implementation
  • NIOS II
  • VDF

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition
  • Software

Cite this

Boudabous, A., Ben Atitallah, A., Kadionik, P., Khriji, L., & Masmoudi, N. (2008). FPGA codesign implementation of vector directional filter. In 2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008 [4743773] https://doi.org/10.1109/IPTA.2008.4743773

FPGA codesign implementation of vector directional filter. / Boudabous, A.; Ben Atitallah, A.; Kadionik, P.; Khriji, L.; Masmoudi, N.

2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008. 2008. 4743773.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Boudabous, A, Ben Atitallah, A, Kadionik, P, Khriji, L & Masmoudi, N 2008, FPGA codesign implementation of vector directional filter. in 2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008., 4743773, 2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008, Sousse, Tunisia, 11/23/08. https://doi.org/10.1109/IPTA.2008.4743773
Boudabous A, Ben Atitallah A, Kadionik P, Khriji L, Masmoudi N. FPGA codesign implementation of vector directional filter. In 2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008. 2008. 4743773 https://doi.org/10.1109/IPTA.2008.4743773
Boudabous, A. ; Ben Atitallah, A. ; Kadionik, P. ; Khriji, L. ; Masmoudi, N. / FPGA codesign implementation of vector directional filter. 2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008. 2008.
@inproceedings{2b0cb8b619134390941a12269729f151,
title = "FPGA codesign implementation of vector directional filter",
abstract = "Recently, Vector Directional Filter (VDF) have been developed either as software based applications or hardware using DSP (digital single processing) technologies. In this paper, we present a new efficient hardware/software (HW/SW) codesign implementation of the VDF using embedded system development board. By means of VHDL language, hardware accelerator including VDF algorithm is implemented with fast pipelined architecture. The remaining parts were realized in software using NIOS II softcore processor and Clinux as operating system. Experimental results confirm that the use of hardware accelerator gives good results concerning image quality and filtering speed.",
keywords = "Color image, Embedded system, FPGA implementation, NIOS II, VDF",
author = "A. Boudabous and {Ben Atitallah}, A. and P. Kadionik and L. Khriji and N. Masmoudi",
year = "2008",
doi = "10.1109/IPTA.2008.4743773",
language = "English",
isbn = "9781424433223",
booktitle = "2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008",

}

TY - GEN

T1 - FPGA codesign implementation of vector directional filter

AU - Boudabous, A.

AU - Ben Atitallah, A.

AU - Kadionik, P.

AU - Khriji, L.

AU - Masmoudi, N.

PY - 2008

Y1 - 2008

N2 - Recently, Vector Directional Filter (VDF) have been developed either as software based applications or hardware using DSP (digital single processing) technologies. In this paper, we present a new efficient hardware/software (HW/SW) codesign implementation of the VDF using embedded system development board. By means of VHDL language, hardware accelerator including VDF algorithm is implemented with fast pipelined architecture. The remaining parts were realized in software using NIOS II softcore processor and Clinux as operating system. Experimental results confirm that the use of hardware accelerator gives good results concerning image quality and filtering speed.

AB - Recently, Vector Directional Filter (VDF) have been developed either as software based applications or hardware using DSP (digital single processing) technologies. In this paper, we present a new efficient hardware/software (HW/SW) codesign implementation of the VDF using embedded system development board. By means of VHDL language, hardware accelerator including VDF algorithm is implemented with fast pipelined architecture. The remaining parts were realized in software using NIOS II softcore processor and Clinux as operating system. Experimental results confirm that the use of hardware accelerator gives good results concerning image quality and filtering speed.

KW - Color image

KW - Embedded system

KW - FPGA implementation

KW - NIOS II

KW - VDF

UR - http://www.scopus.com/inward/record.url?scp=62949193605&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=62949193605&partnerID=8YFLogxK

U2 - 10.1109/IPTA.2008.4743773

DO - 10.1109/IPTA.2008.4743773

M3 - Conference contribution

AN - SCOPUS:62949193605

SN - 9781424433223

BT - 2008 1st International Workshops on Image Processing Theory, Tools and Applications, IPTA 2008

ER -