Abstract
Neuromorphic algorithms for computer-based vision may be the next step towards improving the way computers gather and interpret visual information. However, these algorithms typically have high computational demands making them difficult to deploy in embedded environments where power consumption is equally as important as performance. In this paper, we present an embedded implementation of a ventral visual pathway model, HMAX. We describe an embedded FPGA system that implements the model, as well as accelerator engines necessary to ensure adequate performance. The final system is shown to operate within a power budget of 3W while achieving up to 16.5X speedup over a pure embedded processor implementation.
| Original language | English |
|---|---|
| Title of host publication | Conference Record of the 45th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2011 |
| Pages | 751-755 |
| Number of pages | 5 |
| DOIs | |
| Publication status | Published - 2011 |
| Event | 45th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2011 - Pacific Grove, CA, United States Duration: Nov 6 2011 → Nov 9 2011 |
Other
| Other | 45th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2011 |
|---|---|
| Country | United States |
| City | Pacific Grove, CA |
| Period | 11/6/11 → 11/9/11 |
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Keywords
- Embedded Hardware
- FPGA
- Neuromorphic vision algorithms
- Signal Processing Hardware
ASJC Scopus subject areas
- Signal Processing
- Computer Networks and Communications
Cite this
FPGA-accelerator system for computing biologically inspired feature extraction models. / DeBole, Michael; Xiao, Yang; Yu, Chi Li; Al Maashri, Ahmed; Cotter, Matthew; Chakrabarti, Chaitali; Narayanan, Vijaykrishnan.
Conference Record of the 45th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2011. 2011. p. 751-755 6190106.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - FPGA-accelerator system for computing biologically inspired feature extraction models
AU - DeBole, Michael
AU - Xiao, Yang
AU - Yu, Chi Li
AU - Al Maashri, Ahmed
AU - Cotter, Matthew
AU - Chakrabarti, Chaitali
AU - Narayanan, Vijaykrishnan
PY - 2011
Y1 - 2011
N2 - Neuromorphic algorithms for computer-based vision may be the next step towards improving the way computers gather and interpret visual information. However, these algorithms typically have high computational demands making them difficult to deploy in embedded environments where power consumption is equally as important as performance. In this paper, we present an embedded implementation of a ventral visual pathway model, HMAX. We describe an embedded FPGA system that implements the model, as well as accelerator engines necessary to ensure adequate performance. The final system is shown to operate within a power budget of 3W while achieving up to 16.5X speedup over a pure embedded processor implementation.
AB - Neuromorphic algorithms for computer-based vision may be the next step towards improving the way computers gather and interpret visual information. However, these algorithms typically have high computational demands making them difficult to deploy in embedded environments where power consumption is equally as important as performance. In this paper, we present an embedded implementation of a ventral visual pathway model, HMAX. We describe an embedded FPGA system that implements the model, as well as accelerator engines necessary to ensure adequate performance. The final system is shown to operate within a power budget of 3W while achieving up to 16.5X speedup over a pure embedded processor implementation.
KW - Embedded Hardware
KW - FPGA
KW - Neuromorphic vision algorithms
KW - Signal Processing Hardware
UR - http://www.scopus.com/inward/record.url?scp=84861309075&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84861309075&partnerID=8YFLogxK
U2 - 10.1109/ACSSC.2011.6190106
DO - 10.1109/ACSSC.2011.6190106
M3 - Conference contribution
AN - SCOPUS:84861309075
SN - 9781467303231
SP - 751
EP - 755
BT - Conference Record of the 45th Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2011
ER -