Design of a tokenless architecture for parallel computations using associative dataflow processor

Tariq Jamil*, R. G. Deshmukh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The limitations and weaknesses associated with control-flow and data-flow are described, leading to the description of the proposed concept of associative dataflow. Simulation results of existing dataflow systems are compared with associative dataflow model to support the fact that the new model of computation provides faster execution time and better ALU utilization than the conventional models. Design of an associative data flow system is described by providing as much details as can possibly be incorporated to understand the concept with reference to existing computer systems. Lastly, specifications of the designed system are outlined by listing important characteristics of the associative dataflow system.

Original languageEnglish
Title of host publicationConference Proceedings - IEEE SOUTHEASTCON
Editors Anon
PublisherIEEE
Pages649-656
Number of pages8
Publication statusPublished - 1996
EventProceedings of the 1996 IEEE SOUTHEASTCON Conference - Tampa, FL, USA
Duration: Apr 11 1996Apr 14 1996

Other

OtherProceedings of the 1996 IEEE SOUTHEASTCON Conference
CityTampa, FL, USA
Period4/11/964/14/96

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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