Abstract
To represent complex number as single-unit binary number, a complex binary number utilizing base (-1+j) has been proposed in the scientific literature. In this study, we have designed a nibble-size adder based on this number system using the traditional truth table/Kmap approach and implemented it on Xilinx Virtex FPGAs. We have compared this design with the minimum-delay nibble-size complex binary adders and base-2 binary adders designed using decoder and ripple-carry principle. This research work leads us to the conclusion that the complex binary is a viable number system for designing Arithmetic and Logic Unit (ALU) of today's microprocessors.
Original language | English |
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Pages (from-to) | 1813-1828 |
Number of pages | 16 |
Journal | Journal of Engineering and Applied Sciences |
Volume | 13 |
Issue number | 7 |
DOIs | |
Publication status | Published - 2018 |
Keywords
- Bimq complex numbers
- Complex bmary adder
- FPGA
- Logism Software
- Microprocessors
- Utilizmg
ASJC Scopus subject areas
- Engineering(all)