Abstract
To represent complex number as single-unit binary number, a complex binary number utilizing base (-1+j) has been proposed in the scientific literature. In this study, we have designed a nibble-size adder based on this number system using the traditional truth table/Kmap approach and implemented it on Xilinx Virtex FPGAs. We have compared this design with the minimum-delay nibble-size complex binary adders and base-2 binary adders designed using decoder and ripple-carry principle. This research work leads us to the conclusion that the complex binary is a viable number system for designing Arithmetic and Logic Unit (ALU) of today's microprocessors.
| Original language | English |
|---|---|
| Pages (from-to) | 1813-1828 |
| Number of pages | 16 |
| Journal | Journal of Engineering and Applied Sciences |
| Volume | 13 |
| Issue number | 7 |
| DOIs | |
| Publication status | Published - Jan 1 2018 |
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Keywords
- Bimq complex numbers
- Complex bmary adder
- FPGA
- Logism Software
- Microprocessors
- Utilizmg
ASJC Scopus subject areas
- Engineering(all)
Cite this
Design and implementation of a complex binary adder. / Jamil, Tariq; Medhat Awadalla, H.; Mohammad, Iftaquaruddin.
In: Journal of Engineering and Applied Sciences, Vol. 13, No. 7, 01.01.2018, p. 1813-1828.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Design and implementation of a complex binary adder
AU - Jamil, Tariq
AU - Medhat Awadalla, H.
AU - Mohammad, Iftaquaruddin
PY - 2018/1/1
Y1 - 2018/1/1
N2 - To represent complex number as single-unit binary number, a complex binary number utilizing base (-1+j) has been proposed in the scientific literature. In this study, we have designed a nibble-size adder based on this number system using the traditional truth table/Kmap approach and implemented it on Xilinx Virtex FPGAs. We have compared this design with the minimum-delay nibble-size complex binary adders and base-2 binary adders designed using decoder and ripple-carry principle. This research work leads us to the conclusion that the complex binary is a viable number system for designing Arithmetic and Logic Unit (ALU) of today's microprocessors.
AB - To represent complex number as single-unit binary number, a complex binary number utilizing base (-1+j) has been proposed in the scientific literature. In this study, we have designed a nibble-size adder based on this number system using the traditional truth table/Kmap approach and implemented it on Xilinx Virtex FPGAs. We have compared this design with the minimum-delay nibble-size complex binary adders and base-2 binary adders designed using decoder and ripple-carry principle. This research work leads us to the conclusion that the complex binary is a viable number system for designing Arithmetic and Logic Unit (ALU) of today's microprocessors.
KW - Bimq complex numbers
KW - Complex bmary adder
KW - FPGA
KW - Logism Software
KW - Microprocessors
KW - Utilizmg
UR - http://www.scopus.com/inward/record.url?scp=85048173803&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048173803&partnerID=8YFLogxK
U2 - 10.3923/jeasci.2018.1813.1828
DO - 10.3923/jeasci.2018.1813.1828
M3 - Article
AN - SCOPUS:85048173803
VL - 13
SP - 1813
EP - 1828
JO - Journal of Engineering and Applied Sciences
JF - Journal of Engineering and Applied Sciences
SN - 1816-949X
IS - 7
ER -