Design and implementation of a complex binary adder

Tariq Jamil, H. Medhat Awadalla, Iftaquaruddin Mohammad

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

To represent complex number as single-unit binary number, a complex binary number utilizing base (-1+j) has been proposed in the scientific literature. In this study, we have designed a nibble-size adder based on this number system using the traditional truth table/Kmap approach and implemented it on Xilinx Virtex FPGAs. We have compared this design with the minimum-delay nibble-size complex binary adders and base-2 binary adders designed using decoder and ripple-carry principle. This research work leads us to the conclusion that the complex binary is a viable number system for designing Arithmetic and Logic Unit (ALU) of today's microprocessors.

Original languageEnglish
Pages (from-to)1813-1828
Number of pages16
JournalJournal of Engineering and Applied Sciences
Volume13
Issue number7
DOIs
Publication statusPublished - Jan 1 2018

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Adders
Numbering systems
Field programmable gate arrays (FPGA)
Microprocessor chips

Keywords

  • Bimq complex numbers
  • Complex bmary adder
  • FPGA
  • Logism Software
  • Microprocessors
  • Utilizmg

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Design and implementation of a complex binary adder. / Jamil, Tariq; Medhat Awadalla, H.; Mohammad, Iftaquaruddin.

In: Journal of Engineering and Applied Sciences, Vol. 13, No. 7, 01.01.2018, p. 1813-1828.

Research output: Contribution to journalArticle

Jamil, Tariq ; Medhat Awadalla, H. ; Mohammad, Iftaquaruddin. / Design and implementation of a complex binary adder. In: Journal of Engineering and Applied Sciences. 2018 ; Vol. 13, No. 7. pp. 1813-1828.
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