In a multicomputer network, the channel bandwidth is greatly constrained by implementation technology. Two important constraints have been identified in the literature, each appropriate for a particular technology: wiring density limits dominate in VLSI and pin-out in multiple-chip implementations. Most existing interconnection networks are categorized as either direct or indirect (multi-stage) topologies, the mesh and binary n-cube being examples of the former category, the omega and banyan networks of the latter. This paper argues that direct networks based on hypergraph topologies have characteristics which make them particularly appropriate for use in future high-performance parallel systems. The authors have recently introduced a regular multidimensional hypergraph network, called the Distributed Crossbar Switch Hypermesh (DCSH), which has topological properties that permit a relaxation of bandwidth constraints, and which has important topological and performance advantages over direct graph networks. This paper compares the DCSH to multi-stage networks, under both VLSI and multiple-chip technological constraints. The results suggest that in both cases, with a realistic model which includes routing delays through intermediate nodes, the DCSH exhibits superior performance across a wide range of traffic loads.
ASJC Scopus subject areas
- Computer Science(all)