C37. Updating multicore processor simulator to support dynamic design in fetch stage

H. G. Konsowa, E. M. Saad, M. H A Awadalla

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

During the early design space exploration phase of the microprocessor design process, a variety of enhancements and design options are evaluated by analyzing the performance model of the microprocessor. Current multicore processor is based on complex designs, integrating different components on a single chip, such as hardware threads, processor cores, memory hierarchy or interconnection networks. The permanent need to enhance the performance of multicore motivates the development of dynamic design, using historical data of previous runs to predict new value of architecture parameter. Some basic notions multicore processors architectures are affected by the problem of long-latency instructions stalling the processor pipeline. In this paper, the simulation multicore tool, multi2sim is adapted to cope with multicore processor dynamic design by adding dynamic feature in the policy of thread selection in fetch stage.

Original languageEnglish
Title of host publicationNational Radio Science Conference, NRSC, Proceedings
Pages471-476
Number of pages6
DOIs
Publication statusPublished - 2012
Event2012 29th National Radio Science Conference, NRSC 2012 - Cairo, Egypt
Duration: Apr 10 2012Apr 12 2012

Other

Other2012 29th National Radio Science Conference, NRSC 2012
CountryEgypt
CityCairo
Period4/10/124/12/12

Fingerprint

simulators
central processing units
Simulators
threads
microprocessors
Microprocessor chips
stalling
space exploration
Computer hardware
hierarchies
hardware
education
Pipelines
chips
Data storage equipment
augmentation
simulation

Keywords

  • Fetch policy
  • Multicore design
  • Performance
  • Simulation architecture

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials

Cite this

Konsowa, H. G., Saad, E. M., & Awadalla, M. H. A. (2012). C37. Updating multicore processor simulator to support dynamic design in fetch stage. In National Radio Science Conference, NRSC, Proceedings (pp. 471-476). [6208555] https://doi.org/10.1109/NRSC.2012.6208555

C37. Updating multicore processor simulator to support dynamic design in fetch stage. / Konsowa, H. G.; Saad, E. M.; Awadalla, M. H A.

National Radio Science Conference, NRSC, Proceedings. 2012. p. 471-476 6208555.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Konsowa, HG, Saad, EM & Awadalla, MHA 2012, C37. Updating multicore processor simulator to support dynamic design in fetch stage. in National Radio Science Conference, NRSC, Proceedings., 6208555, pp. 471-476, 2012 29th National Radio Science Conference, NRSC 2012, Cairo, Egypt, 4/10/12. https://doi.org/10.1109/NRSC.2012.6208555
Konsowa HG, Saad EM, Awadalla MHA. C37. Updating multicore processor simulator to support dynamic design in fetch stage. In National Radio Science Conference, NRSC, Proceedings. 2012. p. 471-476. 6208555 https://doi.org/10.1109/NRSC.2012.6208555
Konsowa, H. G. ; Saad, E. M. ; Awadalla, M. H A. / C37. Updating multicore processor simulator to support dynamic design in fetch stage. National Radio Science Conference, NRSC, Proceedings. 2012. pp. 471-476
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