Abstract
During the early design space exploration phase of the microprocessor design process, a variety of enhancements and design options are evaluated by analyzing the performance model of the microprocessor. Current multicore processor is based on complex designs, integrating different components on a single chip, such as hardware threads, processor cores, memory hierarchy or interconnection networks. The permanent need to enhance the performance of multicore motivates the development of dynamic design, using historical data of previous runs to predict new value of architecture parameter. Some basic notions multicore processors architectures are affected by the problem of long-latency instructions stalling the processor pipeline. In this paper, the simulation multicore tool, multi2sim is adapted to cope with multicore processor dynamic design by adding dynamic feature in the policy of thread selection in fetch stage.
| Original language | English |
|---|---|
| Title of host publication | National Radio Science Conference, NRSC, Proceedings |
| Pages | 471-476 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 2012 29th National Radio Science Conference, NRSC 2012 - Cairo, Egypt Duration: Apr 10 2012 → Apr 12 2012 |
Other
| Other | 2012 29th National Radio Science Conference, NRSC 2012 |
|---|---|
| Country | Egypt |
| City | Cairo |
| Period | 4/10/12 → 4/12/12 |
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Keywords
- Fetch policy
- Multicore design
- Performance
- Simulation architecture
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Condensed Matter Physics
- Electronic, Optical and Magnetic Materials
Cite this
C37. Updating multicore processor simulator to support dynamic design in fetch stage. / Konsowa, H. G.; Saad, E. M.; Awadalla, M. H A.
National Radio Science Conference, NRSC, Proceedings. 2012. p. 471-476 6208555.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - C37. Updating multicore processor simulator to support dynamic design in fetch stage
AU - Konsowa, H. G.
AU - Saad, E. M.
AU - Awadalla, M. H A
PY - 2012
Y1 - 2012
N2 - During the early design space exploration phase of the microprocessor design process, a variety of enhancements and design options are evaluated by analyzing the performance model of the microprocessor. Current multicore processor is based on complex designs, integrating different components on a single chip, such as hardware threads, processor cores, memory hierarchy or interconnection networks. The permanent need to enhance the performance of multicore motivates the development of dynamic design, using historical data of previous runs to predict new value of architecture parameter. Some basic notions multicore processors architectures are affected by the problem of long-latency instructions stalling the processor pipeline. In this paper, the simulation multicore tool, multi2sim is adapted to cope with multicore processor dynamic design by adding dynamic feature in the policy of thread selection in fetch stage.
AB - During the early design space exploration phase of the microprocessor design process, a variety of enhancements and design options are evaluated by analyzing the performance model of the microprocessor. Current multicore processor is based on complex designs, integrating different components on a single chip, such as hardware threads, processor cores, memory hierarchy or interconnection networks. The permanent need to enhance the performance of multicore motivates the development of dynamic design, using historical data of previous runs to predict new value of architecture parameter. Some basic notions multicore processors architectures are affected by the problem of long-latency instructions stalling the processor pipeline. In this paper, the simulation multicore tool, multi2sim is adapted to cope with multicore processor dynamic design by adding dynamic feature in the policy of thread selection in fetch stage.
KW - Fetch policy
KW - Multicore design
KW - Performance
KW - Simulation architecture
UR - http://www.scopus.com/inward/record.url?scp=84862872750&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84862872750&partnerID=8YFLogxK
U2 - 10.1109/NRSC.2012.6208555
DO - 10.1109/NRSC.2012.6208555
M3 - Conference contribution
SN - 9781467318853
SP - 471
EP - 476
BT - National Radio Science Conference, NRSC, Proceedings
ER -