C26. An integrated power-efficient mapping and routing technique for mesh-based networks-on-chip

El Sayed M Saad, Sameh A. Salem, Medhat H. Awadalla, Ahmed M. Mostafa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As technology moves towards multi-core system-on-chips (SoCs), networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. One of the most trade-off aspects in the design of NoCs is the improvement of the network performance, in terms of throughput and latency, while minimizing power consumption. This paper proposes an integrated power-efficient mapping and routing technique for mesh-based Networks-on-Chip. This technique combines an oblivious, path-diverse, minimal routing algorithm with a mapping approach that achieves the lowest power consumption in terms of the communication traffic on the global interconnection links. The robustness and reliability of the proposed technique is verified in the context of four different video processing applications: MPEG4, VOPD, MWD, and PIP. The experimental results show that the proposed integrated technique significantly improves network performance and power consumption.

Original languageEnglish
Title of host publicationNational Radio Science Conference, NRSC, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages359-369
Number of pages11
Volume2013-January
DOIs
Publication statusPublished - 2013
Event30th National Radio Science Conference, NRSC 2013 - Cairo, Egypt
Duration: Apr 16 2013Apr 18 2013

Other

Other30th National Radio Science Conference, NRSC 2013
CountryEgypt
CityCairo
Period4/16/134/18/13

Fingerprint

mesh
Electric power utilization
chips
Network performance
Routing algorithms
Telecommunication traffic
Telecommunication links
Throughput
traffic
emerging
communication
Processing
Network-on-chip
System-on-chip

Keywords

  • Mapping technique
  • Networks-on-chip
  • Power-efficient
  • Routing algorithm

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials

Cite this

Saad, E. S. M., Salem, S. A., Awadalla, M. H., & Mostafa, A. M. (2013). C26. An integrated power-efficient mapping and routing technique for mesh-based networks-on-chip. In National Radio Science Conference, NRSC, Proceedings (Vol. 2013-January, pp. 359-369). [6587934] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NRSC.2013.6587934

C26. An integrated power-efficient mapping and routing technique for mesh-based networks-on-chip. / Saad, El Sayed M; Salem, Sameh A.; Awadalla, Medhat H.; Mostafa, Ahmed M.

National Radio Science Conference, NRSC, Proceedings. Vol. 2013-January Institute of Electrical and Electronics Engineers Inc., 2013. p. 359-369 6587934.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Saad, ESM, Salem, SA, Awadalla, MH & Mostafa, AM 2013, C26. An integrated power-efficient mapping and routing technique for mesh-based networks-on-chip. in National Radio Science Conference, NRSC, Proceedings. vol. 2013-January, 6587934, Institute of Electrical and Electronics Engineers Inc., pp. 359-369, 30th National Radio Science Conference, NRSC 2013, Cairo, Egypt, 4/16/13. https://doi.org/10.1109/NRSC.2013.6587934
Saad ESM, Salem SA, Awadalla MH, Mostafa AM. C26. An integrated power-efficient mapping and routing technique for mesh-based networks-on-chip. In National Radio Science Conference, NRSC, Proceedings. Vol. 2013-January. Institute of Electrical and Electronics Engineers Inc. 2013. p. 359-369. 6587934 https://doi.org/10.1109/NRSC.2013.6587934
Saad, El Sayed M ; Salem, Sameh A. ; Awadalla, Medhat H. ; Mostafa, Ahmed M. / C26. An integrated power-efficient mapping and routing technique for mesh-based networks-on-chip. National Radio Science Conference, NRSC, Proceedings. Vol. 2013-January Institute of Electrical and Electronics Engineers Inc., 2013. pp. 359-369
@inproceedings{3e6b785715fd40e08cfb2dca49aff1b8,
title = "C26. An integrated power-efficient mapping and routing technique for mesh-based networks-on-chip",
abstract = "As technology moves towards multi-core system-on-chips (SoCs), networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. One of the most trade-off aspects in the design of NoCs is the improvement of the network performance, in terms of throughput and latency, while minimizing power consumption. This paper proposes an integrated power-efficient mapping and routing technique for mesh-based Networks-on-Chip. This technique combines an oblivious, path-diverse, minimal routing algorithm with a mapping approach that achieves the lowest power consumption in terms of the communication traffic on the global interconnection links. The robustness and reliability of the proposed technique is verified in the context of four different video processing applications: MPEG4, VOPD, MWD, and PIP. The experimental results show that the proposed integrated technique significantly improves network performance and power consumption.",
keywords = "Mapping technique, Networks-on-chip, Power-efficient, Routing algorithm",
author = "Saad, {El Sayed M} and Salem, {Sameh A.} and Awadalla, {Medhat H.} and Mostafa, {Ahmed M.}",
year = "2013",
doi = "10.1109/NRSC.2013.6587934",
language = "English",
volume = "2013-January",
pages = "359--369",
booktitle = "National Radio Science Conference, NRSC, Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

TY - GEN

T1 - C26. An integrated power-efficient mapping and routing technique for mesh-based networks-on-chip

AU - Saad, El Sayed M

AU - Salem, Sameh A.

AU - Awadalla, Medhat H.

AU - Mostafa, Ahmed M.

PY - 2013

Y1 - 2013

N2 - As technology moves towards multi-core system-on-chips (SoCs), networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. One of the most trade-off aspects in the design of NoCs is the improvement of the network performance, in terms of throughput and latency, while minimizing power consumption. This paper proposes an integrated power-efficient mapping and routing technique for mesh-based Networks-on-Chip. This technique combines an oblivious, path-diverse, minimal routing algorithm with a mapping approach that achieves the lowest power consumption in terms of the communication traffic on the global interconnection links. The robustness and reliability of the proposed technique is verified in the context of four different video processing applications: MPEG4, VOPD, MWD, and PIP. The experimental results show that the proposed integrated technique significantly improves network performance and power consumption.

AB - As technology moves towards multi-core system-on-chips (SoCs), networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. One of the most trade-off aspects in the design of NoCs is the improvement of the network performance, in terms of throughput and latency, while minimizing power consumption. This paper proposes an integrated power-efficient mapping and routing technique for mesh-based Networks-on-Chip. This technique combines an oblivious, path-diverse, minimal routing algorithm with a mapping approach that achieves the lowest power consumption in terms of the communication traffic on the global interconnection links. The robustness and reliability of the proposed technique is verified in the context of four different video processing applications: MPEG4, VOPD, MWD, and PIP. The experimental results show that the proposed integrated technique significantly improves network performance and power consumption.

KW - Mapping technique

KW - Networks-on-chip

KW - Power-efficient

KW - Routing algorithm

UR - http://www.scopus.com/inward/record.url?scp=84982706063&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84982706063&partnerID=8YFLogxK

U2 - 10.1109/NRSC.2013.6587934

DO - 10.1109/NRSC.2013.6587934

M3 - Conference contribution

AN - SCOPUS:84982706063

VL - 2013-January

SP - 359

EP - 369

BT - National Radio Science Conference, NRSC, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

ER -