C26. An integrated power-efficient mapping and routing technique for mesh-based networks-on-chip

As technology moves towards multi-core system-on-chips (SoCs), networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. One of the most trade-off aspects in the design of NoCs is the improvement of the network performance, in terms of throughput and latency, while minimizing power consumption. This paper proposes an integrated power-efficient mapping and routing technique for mesh-based Networks-on-Chip. This technique combines an oblivious, path-diverse, minimal routing algorithm with a mapping approach that achieves the lowest power consumption in terms of the communication traffic on the global interconnection links. The robustness and reliability of the proposed technique is verified in the context of four different video processing applications: MPEG4, VOPD, MWD, and PIP. The experimental results show that the proposed integrated technique significantly improves network performance and power consumption.