Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator

Anis Boudabous; Ahmed Ben Atitallah; Lazhar Khriji; Nouri Masmoudi

doi:10.1109/DTIS.2012.6232968

Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator

Anis Boudabous^*, Ahmed Ben Atitallah, Lazhar Khriji, Nouri Masmoudi

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, a new hardware implementation of the Border-Preserving Interpolator is presented. The object of this proposed work is to achieve significant run time performance using a hardware development board. It also demonstrates consistent image quality performance among a variety of images. This validation show that our implementation based on HW/SW design speeds up the interpolation process as well as preserving a high image quality.

Original language	English
Title of host publication	7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012
DOIs	https://doi.org/10.1109/DTIS.2012.6232968
Publication status	Published - 2012
Event	7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012 - Gammarth, Tunisia Duration: May 16 2012 → May 18 2012

Publication series

Name	7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012

Other

Other	7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012
Country/Territory	Tunisia
City	Gammarth
Period	5/16/12 → 5/18/12

Keywords

FPGA
HW/SW
Nonlinear interpolation
Reconfigurable Architecture
color image

ASJC Scopus subject areas

Control and Systems Engineering

Access to Document

10.1109/DTIS.2012.6232968

Cite this

Boudabous, A., Ben Atitallah, A., Khriji, L., & Masmoudi, N. (2012). Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator. In 7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012 Article 6232968 (7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012). https://doi.org/10.1109/DTIS.2012.6232968

Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator. / Boudabous, Anis; Ben Atitallah, Ahmed; Khriji, Lazhar et al.
7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012. 2012. 6232968 (7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Boudabous, A, Ben Atitallah, A, Khriji, L & Masmoudi, N 2012, Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator. in 7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012., 6232968, 7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012, 7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012, Gammarth, Tunisia, 5/16/12. https://doi.org/10.1109/DTIS.2012.6232968

Boudabous A, Ben Atitallah A, Khriji L, Masmoudi N. Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator. In 7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012. 2012. 6232968. (7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012). doi: 10.1109/DTIS.2012.6232968

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Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator

Abstract

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Keywords

ASJC Scopus subject areas

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