Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator

Anis Boudabous, Ahmed Ben Atitallah, Lazhar Khriji, Nouri Masmoudi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, a new hardware implementation of the Border-Preserving Interpolator is presented. The object of this proposed work is to achieve significant run time performance using a hardware development board. It also demonstrates consistent image quality performance among a variety of images. This validation show that our implementation based on HW/SW design speeds up the interpolation process as well as preserving a high image quality.

Original languageEnglish
Title of host publication7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012
DOIs
Publication statusPublished - 2012
Event7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012 - Gammarth, Tunisia
Duration: May 16 2012May 18 2012

Other

Other7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012
CountryTunisia
CityGammarth
Period5/16/125/18/12

Keywords

  • color image
  • FPGA
  • HW/SW
  • Nonlinear interpolation
  • Reconfigurable Architecture

ASJC Scopus subject areas

  • Control and Systems Engineering

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  • Cite this

    Boudabous, A., Ben Atitallah, A., Khriji, L., & Masmoudi, N. (2012). Architecture and HW/SW validation of nonlinear Border-Preserving Interpolator. In 7th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2012 [6232968] https://doi.org/10.1109/DTIS.2012.6232968