An efficient hardware implementation of parallel EBCOT algorithm for JPEG 2000

Taoufik Saidani*, Mohamed Atri, Lazhar Khriji, Rached Tourki

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)


With the augmentation in multimedia technology, demand for high-speed real-time image compression systems has also increased. JPEG 2000 still image compression standard is developed to accommodate such application requirements. Embedded block coding with optimal truncation (EBCOT) is an essential and computationally very demanding part of the compression process of JPEG 2000 image compression standard. Various applications, such as satellite imagery, medical imaging, digital cinema, and others, require high speed and performance EBCOT architecture. In JPEG 2000 standard, the context formation block of EBCOT tier-1 contains high complexity computation and also becomes the bottleneck in this system. In this paper, we propose a fast and efficient VLSI hardware architecture design of context formation for EBCOT tier-1. A high-speed parallel bit-plane coding (BPC) hardware architecture for the EBCOT module in JPEG 2000 is proposed and implemented. Experimental results show that our design outperforms well-known techniques with respect to the processing time. It can reach 70 % reduction when compared to bit plane sequential processing.

Original languageEnglish
Pages (from-to)63-74
Number of pages12
JournalJournal of Real-Time Image Processing
Issue number1
Publication statusPublished - Jan 1 2016


  • Bit-plane coding
  • EBCOT algorithm
  • FPGA implementation
  • JPEG 2000
  • VHDL

ASJC Scopus subject areas

  • Information Systems


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