An efficient cache organization for on-chip multiprocessor networks

Medhat H. Awadalla, Ahmed Sadek

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased. By adding many computing resources to build a system in System-on-Chip, its interconnection between each other becomes a challenging issue. This paper focuses on the interconnection design issues of area, power and performance of chip multiprocessors with shared cache memory. It shows that having a shared cache memory contributes to the performance improvement; however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores. This paper proposes an architectural paradigm in an attempt to gain smaller area occupation allowing more space for an additional cache memory. It also reduces power consumption compared to the existing crossbar architecture. Furthermore, the paper modified the typical MESI cache coherence algorithm to be tailored for the suggested architecture. The experimental results show that the developed architecture produces less broadcast operations compared to the typical algorithm.

Original languageEnglish
Pages (from-to)503-517
Number of pages15
JournalInternational Journal of Electrical and Computer Engineering
Volume5
Issue number3
Publication statusPublished - Jun 1 2015

Fingerprint

Cache memory
Electric power utilization

Keywords

  • Chip multi processors
  • Interconnection mechanisms
  • Shared cache memory

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science(all)

Cite this

An efficient cache organization for on-chip multiprocessor networks. / Awadalla, Medhat H.; Sadek, Ahmed.

In: International Journal of Electrical and Computer Engineering, Vol. 5, No. 3, 01.06.2015, p. 503-517.

Research output: Contribution to journalArticle

@article{051d97c0bafc4fcb9ee1ddffb02e373a,
title = "An efficient cache organization for on-chip multiprocessor networks",
abstract = "To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased. By adding many computing resources to build a system in System-on-Chip, its interconnection between each other becomes a challenging issue. This paper focuses on the interconnection design issues of area, power and performance of chip multiprocessors with shared cache memory. It shows that having a shared cache memory contributes to the performance improvement; however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores. This paper proposes an architectural paradigm in an attempt to gain smaller area occupation allowing more space for an additional cache memory. It also reduces power consumption compared to the existing crossbar architecture. Furthermore, the paper modified the typical MESI cache coherence algorithm to be tailored for the suggested architecture. The experimental results show that the developed architecture produces less broadcast operations compared to the typical algorithm.",
keywords = "Chip multi processors, Interconnection mechanisms, Shared cache memory",
author = "Awadalla, {Medhat H.} and Ahmed Sadek",
year = "2015",
month = "6",
day = "1",
language = "English",
volume = "5",
pages = "503--517",
journal = "International Journal of Electrical and Computer Engineering",
issn = "2088-8708",
publisher = "Institute of Advanced Engineering and Science (IAES)",
number = "3",

}

TY - JOUR

T1 - An efficient cache organization for on-chip multiprocessor networks

AU - Awadalla, Medhat H.

AU - Sadek, Ahmed

PY - 2015/6/1

Y1 - 2015/6/1

N2 - To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased. By adding many computing resources to build a system in System-on-Chip, its interconnection between each other becomes a challenging issue. This paper focuses on the interconnection design issues of area, power and performance of chip multiprocessors with shared cache memory. It shows that having a shared cache memory contributes to the performance improvement; however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores. This paper proposes an architectural paradigm in an attempt to gain smaller area occupation allowing more space for an additional cache memory. It also reduces power consumption compared to the existing crossbar architecture. Furthermore, the paper modified the typical MESI cache coherence algorithm to be tailored for the suggested architecture. The experimental results show that the developed architecture produces less broadcast operations compared to the typical algorithm.

AB - To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased. By adding many computing resources to build a system in System-on-Chip, its interconnection between each other becomes a challenging issue. This paper focuses on the interconnection design issues of area, power and performance of chip multiprocessors with shared cache memory. It shows that having a shared cache memory contributes to the performance improvement; however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores. This paper proposes an architectural paradigm in an attempt to gain smaller area occupation allowing more space for an additional cache memory. It also reduces power consumption compared to the existing crossbar architecture. Furthermore, the paper modified the typical MESI cache coherence algorithm to be tailored for the suggested architecture. The experimental results show that the developed architecture produces less broadcast operations compared to the typical algorithm.

KW - Chip multi processors

KW - Interconnection mechanisms

KW - Shared cache memory

UR - http://www.scopus.com/inward/record.url?scp=84931306817&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84931306817&partnerID=8YFLogxK

M3 - Article

VL - 5

SP - 503

EP - 517

JO - International Journal of Electrical and Computer Engineering

JF - International Journal of Electrical and Computer Engineering

SN - 2088-8708

IS - 3

ER -