An algorithm-architecture co-design framework for gridding reconstruction using FPGAs

Srinidhi Kestur, Kevin Irick, Sungho Park, Ahmed Al Maashri, Vijaykrishnan Narayanan, Chaitaili Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Gridding is a method of interpolating irregularly sampled data on to a uniform grid and is a critical image reconstruction step in several applications which operate on non-Cartesian sampled data. In this paper, we present an algorithm-architecture co-design framework for accelerating gridding using FPGAs. We present a parameterized hardware library for accelerating gridding to support both arbitrary and regular trajectories. We further describe our kernel automation framework which supports several kernel functions through look-up-table (LUT) based Taylor polynomial evaluation. This framework is integrated using an in-house multi-FPGA development platform which provides hardware infrastructure for integrating custom accelerators. Design-space exploration is enabled by an automation flow which allows system generation from an algorithm specification. We further provide several case studies by realizing systems for nonuniform fast Fourier transform (NuFFT) with different parameter sets and porting them on to the BEE3 platform. Results show speedups of more than 16X and 2X over existing CPU and FPGA implementations respectively, and up to 5.5 times higher performance-per-watt over a comparable GPU implementation.

Original languageEnglish
Title of host publication2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
Pages585-590
Number of pages6
Publication statusPublished - 2011
Event2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 - San Diego, CA, United States
Duration: Jun 5 2011Jun 9 2011

Other

Other2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
CountryUnited States
CitySan Diego, CA
Period6/5/116/9/11

Fingerprint

Co-design
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Automation
Hardware
Polynomial Evaluation
Taylor Polynomial
Design Space Exploration
FPGA Implementation
Look-up Table
Image Reconstruction
Fast Fourier transform
Kernel Function
Accelerator
Image reconstruction
Fast Fourier transforms
Particle accelerators
Program processors
Infrastructure
High Performance

Keywords

  • BEE3
  • Cartesian
  • Gridding
  • Nonuniform fast Fourier transform
  • Polar
  • Taylor polynomial evaluation

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation

Cite this

Kestur, S., Irick, K., Park, S., Al Maashri, A., Narayanan, V., & Chakrabarti, C. (2011). An algorithm-architecture co-design framework for gridding reconstruction using FPGAs. In 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 (pp. 585-590). [5981980]

An algorithm-architecture co-design framework for gridding reconstruction using FPGAs. / Kestur, Srinidhi; Irick, Kevin; Park, Sungho; Al Maashri, Ahmed; Narayanan, Vijaykrishnan; Chakrabarti, Chaitaili.

2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. 2011. p. 585-590 5981980.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kestur, S, Irick, K, Park, S, Al Maashri, A, Narayanan, V & Chakrabarti, C 2011, An algorithm-architecture co-design framework for gridding reconstruction using FPGAs. in 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011., 5981980, pp. 585-590, 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011, San Diego, CA, United States, 6/5/11.
Kestur S, Irick K, Park S, Al Maashri A, Narayanan V, Chakrabarti C. An algorithm-architecture co-design framework for gridding reconstruction using FPGAs. In 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. 2011. p. 585-590. 5981980
Kestur, Srinidhi ; Irick, Kevin ; Park, Sungho ; Al Maashri, Ahmed ; Narayanan, Vijaykrishnan ; Chakrabarti, Chaitaili. / An algorithm-architecture co-design framework for gridding reconstruction using FPGAs. 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. 2011. pp. 585-590
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