Achievement of higher testability goals through the modification of shift registers in LFSR-based testing

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Abstract

The paper is devoted to the achievement of higher testability goals in the BIST environment through the modification of shift registers in LFSR-based testing. The aim is here to take the unified view of the effectiveness of various test-generation and response evaluation techniques with BIST capabilities to justify the design of unified built-in testing scheme. With this objective in mind, a comprehensive analysis of the principles involved has been undertaken to evolve an effective design approach for LFSR-based testing of combinational circuits. The proposed unified testing scheme is analysed through the testing of many ICs through a simulation study. Also, the design implementation of the scheme does not require extra hardware.

Original languageEnglish
Pages (from-to)249-260
Number of pages12
JournalInternational Journal of Electronics
Volume82
Issue number3
Publication statusPublished - 1997

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Shift registers
Built-in self test
Testing
Combinatorial circuits
Hardware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

@article{07e22a100a0e419a94f48a027758bc81,
title = "Achievement of higher testability goals through the modification of shift registers in LFSR-based testing",
abstract = "The paper is devoted to the achievement of higher testability goals in the BIST environment through the modification of shift registers in LFSR-based testing. The aim is here to take the unified view of the effectiveness of various test-generation and response evaluation techniques with BIST capabilities to justify the design of unified built-in testing scheme. With this objective in mind, a comprehensive analysis of the principles involved has been undertaken to evolve an effective design approach for LFSR-based testing of combinational circuits. The proposed unified testing scheme is analysed through the testing of many ICs through a simulation study. Also, the design implementation of the scheme does not require extra hardware.",
author = "A. Ahmad",
year = "1997",
language = "English",
volume = "82",
pages = "249--260",
journal = "International Journal of Electronics",
issn = "0020-7217",
publisher = "Taylor and Francis Ltd.",
number = "3",

}

TY - JOUR

T1 - Achievement of higher testability goals through the modification of shift registers in LFSR-based testing

AU - Ahmad, A.

PY - 1997

Y1 - 1997

N2 - The paper is devoted to the achievement of higher testability goals in the BIST environment through the modification of shift registers in LFSR-based testing. The aim is here to take the unified view of the effectiveness of various test-generation and response evaluation techniques with BIST capabilities to justify the design of unified built-in testing scheme. With this objective in mind, a comprehensive analysis of the principles involved has been undertaken to evolve an effective design approach for LFSR-based testing of combinational circuits. The proposed unified testing scheme is analysed through the testing of many ICs through a simulation study. Also, the design implementation of the scheme does not require extra hardware.

AB - The paper is devoted to the achievement of higher testability goals in the BIST environment through the modification of shift registers in LFSR-based testing. The aim is here to take the unified view of the effectiveness of various test-generation and response evaluation techniques with BIST capabilities to justify the design of unified built-in testing scheme. With this objective in mind, a comprehensive analysis of the principles involved has been undertaken to evolve an effective design approach for LFSR-based testing of combinational circuits. The proposed unified testing scheme is analysed through the testing of many ICs through a simulation study. Also, the design implementation of the scheme does not require extra hardware.

UR - http://www.scopus.com/inward/record.url?scp=3342967122&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=3342967122&partnerID=8YFLogxK

M3 - Article

VL - 82

SP - 249

EP - 260

JO - International Journal of Electronics

JF - International Journal of Electronics

SN - 0020-7217

IS - 3

ER -