A scalable multi-FPGA framework for real-time digital signal processing

K. M. Irick, M. Debole, S. Park, A. Al Maashri, S. Kestur, C. L. Yu, N. Vijaykrishnan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

FPGAs have emerged as the preferred platform for implementing real-time signal processing applications. In the sub-45nm technologies, FPGAs offer significant cost and design-time advantages over application-specific custom chips and consume significantly less power than general-purpose processors while maintaining, or improving performance. Moreover, FPGAs are more advantageous than GPUs in their support for control-intensive applications, custom bit-precision operations, and diverse system interface protocols. Nonetheless, a significant inhibitor to the widespread adoption of FPGAs has been the expertise required to effectively realize functional designs that maximize application performance. While there have been several academic and commercial efforts to improve the usability of FPGAs, they have primarily focused on easing the tasks of an expert FPGA designer rather than increasing the usability offered to an application developer. In this work, the design of a scalable algorithmic-level design framework for FPGAs, AlgoFLEX, is described. AlgoFLEX offers rapid algorithmic level composition and exploration while maintaining the performance realizable from a fully custom, albeit difficult and laborious, design effort. The framework masks aspects of accelerator implementation, mapping, and communication while exposing appropriate algorithm tuning facilities to developers and system integrators. The effectiveness of the AlgoFLEX framework is demonstrated by rapidly mapping a class of image and signal processing applications to a multi-FPGA platform.

Original languageEnglish
Title of host publicationMathematics for Signal and Information Processing
Volume7444
DOIs
Publication statusPublished - 2009
EventMathematics for Signal and Information Processing - San Diego, CA, United States
Duration: Aug 2 2009Aug 5 2009

Other

OtherMathematics for Signal and Information Processing
CountryUnited States
CitySan Diego, CA
Period8/2/098/5/09

Fingerprint

Digital signal processing
Field Programmable Gate Array
Signal Processing
Field programmable gate arrays (FPGA)
signal processing
Real-time
photographic developers
platforms
Usability
Signal processing
time signals
integrators
inhibitors
image processing
central processing units
Framework
accelerators
masks
Accelerator
Expertise

Keywords

  • FPGA design
  • Image processing

ASJC Scopus subject areas

  • Applied Mathematics
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics

Cite this

Irick, K. M., Debole, M., Park, S., Al Maashri, A., Kestur, S., Yu, C. L., & Vijaykrishnan, N. (2009). A scalable multi-FPGA framework for real-time digital signal processing. In Mathematics for Signal and Information Processing (Vol. 7444). [744416] https://doi.org/10.1117/12.834177

A scalable multi-FPGA framework for real-time digital signal processing. / Irick, K. M.; Debole, M.; Park, S.; Al Maashri, A.; Kestur, S.; Yu, C. L.; Vijaykrishnan, N.

Mathematics for Signal and Information Processing. Vol. 7444 2009. 744416.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Irick, KM, Debole, M, Park, S, Al Maashri, A, Kestur, S, Yu, CL & Vijaykrishnan, N 2009, A scalable multi-FPGA framework for real-time digital signal processing. in Mathematics for Signal and Information Processing. vol. 7444, 744416, Mathematics for Signal and Information Processing, San Diego, CA, United States, 8/2/09. https://doi.org/10.1117/12.834177
Irick KM, Debole M, Park S, Al Maashri A, Kestur S, Yu CL et al. A scalable multi-FPGA framework for real-time digital signal processing. In Mathematics for Signal and Information Processing. Vol. 7444. 2009. 744416 https://doi.org/10.1117/12.834177
Irick, K. M. ; Debole, M. ; Park, S. ; Al Maashri, A. ; Kestur, S. ; Yu, C. L. ; Vijaykrishnan, N. / A scalable multi-FPGA framework for real-time digital signal processing. Mathematics for Signal and Information Processing. Vol. 7444 2009.
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