A scalable bandwidth aware architecture for connected component labeling

Vikram Sampath Kumar, Kevin Irick, Ahmed Al Maashri, N. Vijaykrishnan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component Labeling architecture that includes a scalable processor that can be tuned to match the I/O bandwidth available in modern embedded computing platforms.

Original languageEnglish
Title of host publicationProceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010
Pages116-121
Number of pages6
DOIs
Publication statusPublished - 2010
EventIEEE Annual Symposium on VLSI, ISVLSI 2010 - Lixouri, Kefalonia, Greece
Duration: Jul 5 2010Jul 7 2010

Other

OtherIEEE Annual Symposium on VLSI, ISVLSI 2010
CountryGreece
CityLixouri, Kefalonia
Period7/5/107/7/10

Keywords

  • Connected component labeling
  • Single-pass
  • Slice processing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A scalable bandwidth aware architecture for connected component labeling'. Together they form a unique fingerprint.

  • Cite this

    Kumar, V. S., Irick, K., Maashri, A. A., & Vijaykrishnan, N. (2010). A scalable bandwidth aware architecture for connected component labeling. In Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010 (pp. 116-121). [5571797] https://doi.org/10.1109/ISVLSI.2010.89