A parallel Gauss-Seidel algorithm on a 3D torus network-on-chip architecture

Khaled Day, Mohammad H. Al-Towaiq

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose an efficient parallel Gauss-Seidel (GS) iterative algorithm for solving large systems of linear equations on a 3-dimensional torus network-on-chip (NoC) architecture. The proposed parallel algorithm is O(Nn2/k3) time complexity for solving a system with matrix of order n on a k×k×k 3D torus NoC architecture with N iterations assuming n and N are large compared to k. We show that under these conditions the proposed parallel GS algorithm has near optimal speedup.

Original languageEnglish
Title of host publicationProceedings - 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages13-16
Number of pages4
ISBN (Print)9781479918706
DOIs
Publication statusPublished - Feb 27 2015
Event2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015 - Amsterdam, Netherlands
Duration: Jan 19 2015 → …

Other

Other2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015
CountryNetherlands
CityAmsterdam
Period1/19/15 → …

Fingerprint

Linear equations
Parallel algorithms
Network-on-chip

Keywords

  • 3D torus
  • Gauss-Seidel
  • linear system of equations
  • network-on-chip
  • parallel algorithm

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Software

Cite this

Day, K., & Al-Towaiq, M. H. (2015). A parallel Gauss-Seidel algorithm on a 3D torus network-on-chip architecture. In Proceedings - 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015 (pp. 13-16). [7051997] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/INA-OCMC.2015.8

A parallel Gauss-Seidel algorithm on a 3D torus network-on-chip architecture. / Day, Khaled; Al-Towaiq, Mohammad H.

Proceedings - 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 13-16 7051997.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Day, K & Al-Towaiq, MH 2015, A parallel Gauss-Seidel algorithm on a 3D torus network-on-chip architecture. in Proceedings - 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015., 7051997, Institute of Electrical and Electronics Engineers Inc., pp. 13-16, 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015, Amsterdam, Netherlands, 1/19/15. https://doi.org/10.1109/INA-OCMC.2015.8
Day K, Al-Towaiq MH. A parallel Gauss-Seidel algorithm on a 3D torus network-on-chip architecture. In Proceedings - 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 13-16. 7051997 https://doi.org/10.1109/INA-OCMC.2015.8
Day, Khaled ; Al-Towaiq, Mohammad H. / A parallel Gauss-Seidel algorithm on a 3D torus network-on-chip architecture. Proceedings - 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 13-16
@inproceedings{4e8ff6b94518416283c81ed0fac332e1,
title = "A parallel Gauss-Seidel algorithm on a 3D torus network-on-chip architecture",
abstract = "We propose an efficient parallel Gauss-Seidel (GS) iterative algorithm for solving large systems of linear equations on a 3-dimensional torus network-on-chip (NoC) architecture. The proposed parallel algorithm is O(Nn2/k3) time complexity for solving a system with matrix of order n on a k×k×k 3D torus NoC architecture with N iterations assuming n and N are large compared to k. We show that under these conditions the proposed parallel GS algorithm has near optimal speedup.",
keywords = "3D torus, Gauss-Seidel, linear system of equations, network-on-chip, parallel algorithm",
author = "Khaled Day and Al-Towaiq, {Mohammad H.}",
year = "2015",
month = "2",
day = "27",
doi = "10.1109/INA-OCMC.2015.8",
language = "English",
isbn = "9781479918706",
pages = "13--16",
booktitle = "Proceedings - 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - A parallel Gauss-Seidel algorithm on a 3D torus network-on-chip architecture

AU - Day, Khaled

AU - Al-Towaiq, Mohammad H.

PY - 2015/2/27

Y1 - 2015/2/27

N2 - We propose an efficient parallel Gauss-Seidel (GS) iterative algorithm for solving large systems of linear equations on a 3-dimensional torus network-on-chip (NoC) architecture. The proposed parallel algorithm is O(Nn2/k3) time complexity for solving a system with matrix of order n on a k×k×k 3D torus NoC architecture with N iterations assuming n and N are large compared to k. We show that under these conditions the proposed parallel GS algorithm has near optimal speedup.

AB - We propose an efficient parallel Gauss-Seidel (GS) iterative algorithm for solving large systems of linear equations on a 3-dimensional torus network-on-chip (NoC) architecture. The proposed parallel algorithm is O(Nn2/k3) time complexity for solving a system with matrix of order n on a k×k×k 3D torus NoC architecture with N iterations assuming n and N are large compared to k. We show that under these conditions the proposed parallel GS algorithm has near optimal speedup.

KW - 3D torus

KW - Gauss-Seidel

KW - linear system of equations

KW - network-on-chip

KW - parallel algorithm

UR - http://www.scopus.com/inward/record.url?scp=84934285764&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84934285764&partnerID=8YFLogxK

U2 - 10.1109/INA-OCMC.2015.8

DO - 10.1109/INA-OCMC.2015.8

M3 - Conference contribution

SN - 9781479918706

SP - 13

EP - 16

BT - Proceedings - 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

ER -