A parallel Gauss-Seidel algorithm on a 3D torus network-on-chip architecture

Khaled Day, Mohammad H. Al-Towaiq

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose an efficient parallel Gauss-Seidel (GS) iterative algorithm for solving large systems of linear equations on a 3-dimensional torus network-on-chip (NoC) architecture. The proposed parallel algorithm is O(Nn2/k3) time complexity for solving a system with matrix of order n on a k×k×k 3D torus NoC architecture with N iterations assuming n and N are large compared to k. We show that under these conditions the proposed parallel GS algorithm has near optimal speedup.

Original languageEnglish
Title of host publicationProceedings - 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages13-16
Number of pages4
ISBN (Print)9781479918706
DOIs
Publication statusPublished - Feb 27 2015
Event2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015 - Amsterdam, Netherlands
Duration: Jan 19 2015 → …

Other

Other2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015
CountryNetherlands
CityAmsterdam
Period1/19/15 → …

Keywords

  • 3D torus
  • Gauss-Seidel
  • linear system of equations
  • network-on-chip
  • parallel algorithm

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Software

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  • Cite this

    Day, K., & Al-Towaiq, M. H. (2015). A parallel Gauss-Seidel algorithm on a 3D torus network-on-chip architecture. In Proceedings - 2015 9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC 2015 (pp. 13-16). [7051997] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/INA-OCMC.2015.8