A heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution

A. Ahmad; S. Ahmad; D. Al-Abri; T. Jamil; M. A K Rizvi

doi:10.1109/ICCCNT.2015.7395238

A heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution

A. Ahmad, S. Ahmad, D. Al-Abri, T. Jamil, M. A K Rizvi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In today's world Built-In Test is the necessity for the designs of digital logic circuits. However, providing solutions with such concept requires cumbersome and typical procedures of designs and because of this majority of the design go without incorporating the features of Built-In Test in the designs. The design procedures further aggravates if optimal design is needed. Hence, in view of this, an idea of a heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution is proposed through this paper.

Original language	English
Title of host publication	6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781479979844
DOIs	https://doi.org/10.1109/ICCCNT.2015.7395238
Publication status	Published - Jan 29 2016
Event	6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015 - Denton, United States Duration: Jul 13 2015 → Jul 15 2015

Other

Other	6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015
Country	United States
City	Denton
Period	7/13/15 → 7/15/15

Keywords

Built-in self-Test
Built-in test
Circuit under test
Design for test
Fault cover
Test sequence

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture

Access to Document

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Cite this

Ahmad, A., Ahmad, S., Al-Abri, D., Jamil, T., & Rizvi, M. A. K. (2016). A heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution. In 6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015 [7395238] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCCNT.2015.7395238

A heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution. / Ahmad, A.; Ahmad, S.; Al-Abri, D.; Jamil, T.; Rizvi, M. A K.

6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7395238.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ahmad, A, Ahmad, S, Al-Abri, D , Jamil, T & Rizvi, MAK 2016, A heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution. in 6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015., 7395238, Institute of Electrical and Electronics Engineers Inc., 6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015, Denton, United States, 7/13/15. https://doi.org/10.1109/ICCCNT.2015.7395238

Ahmad A, Ahmad S, Al-Abri D , Jamil T, Rizvi MAK. A heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution. In 6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7395238 https://doi.org/10.1109/ICCCNT.2015.7395238

@inproceedings{7286039bf4e44df694604c3ddc6180aa,

title = "A heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution",

abstract = "In today's world Built-In Test is the necessity for the designs of digital logic circuits. However, providing solutions with such concept requires cumbersome and typical procedures of designs and because of this majority of the design go without incorporating the features of Built-In Test in the designs. The design procedures further aggravates if optimal design is needed. Hence, in view of this, an idea of a heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution is proposed through this paper.",

keywords = "Built-in self-Test, Built-in test, Circuit under test, Design for test, Fault cover, Test sequence",

author = "A. Ahmad and S. Ahmad and D. Al-Abri and T. Jamil and Rizvi, {M. A K}",

year = "2016",

month = jan,

day = "29",

doi = "10.1109/ICCCNT.2015.7395238",

language = "English",

isbn = "9781479979844",

booktitle = "6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015 ; Conference date: 13-07-2015 Through 15-07-2015",

}

TY - GEN

T1 - A heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution

AU - Ahmad, A.

AU - Ahmad, S.

AU - Al-Abri, D.

AU - Jamil, T.

AU - Rizvi, M. A K

PY - 2016/1/29

Y1 - 2016/1/29

N2 - In today's world Built-In Test is the necessity for the designs of digital logic circuits. However, providing solutions with such concept requires cumbersome and typical procedures of designs and because of this majority of the design go without incorporating the features of Built-In Test in the designs. The design procedures further aggravates if optimal design is needed. Hence, in view of this, an idea of a heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution is proposed through this paper.

AB - In today's world Built-In Test is the necessity for the designs of digital logic circuits. However, providing solutions with such concept requires cumbersome and typical procedures of designs and because of this majority of the design go without incorporating the features of Built-In Test in the designs. The design procedures further aggravates if optimal design is needed. Hence, in view of this, an idea of a heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution is proposed through this paper.

KW - Built-in self-Test

KW - Built-in test

KW - Circuit under test

KW - Design for test

KW - Fault cover

KW - Test sequence

UR - http://www.scopus.com/inward/record.url?scp=84964470871&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84964470871&partnerID=8YFLogxK

U2 - 10.1109/ICCCNT.2015.7395238

DO - 10.1109/ICCCNT.2015.7395238

M3 - Conference contribution

AN - SCOPUS:84964470871

SN - 9781479979844

BT - 6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015

Y2 - 13 July 2015 through 15 July 2015

ER -