A heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution

A. Ahmad, S. Ahmad, D. Al-Abri, T. Jamil, M. A K Rizvi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In today's world Built-In Test is the necessity for the designs of digital logic circuits. However, providing solutions with such concept requires cumbersome and typical procedures of designs and because of this majority of the design go without incorporating the features of Built-In Test in the designs. The design procedures further aggravates if optimal design is needed. Hence, in view of this, an idea of a heuristic approach towards the designs of digital logic circuits in Built-In Test environment with optimal solution is proposed through this paper.

Original languageEnglish
Title of host publication6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479979844
DOIs
Publication statusPublished - Jan 29 2016
Event6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015 - Denton, United States
Duration: Jul 13 2015Jul 15 2015

Other

Other6th International Conference on Computing, Communications and Networking Technologies, ICCCNT 2015
CountryUnited States
CityDenton
Period7/13/157/15/15

Keywords

  • Built-in self-Test
  • Built-in test
  • Circuit under test
  • Design for test
  • Fault cover
  • Test sequence

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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