A hardware architecture for accelerating neuromorphic vision algorithms

A. Al Maashri, M. DeBole, C. L. Yu, V. Narayanan, C. Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Neuromorphic vision algorithms are biologically inspired algorithms that follow the processing that takes place in the visual cortex. These algorithms have proved to match classical computer vision algorithms in classification performance and even outperformed them in some instances. However, neuromorphic algorithms suffer from high complexity leading to poor execution times when running on general purpose processors, making them less attractive for real-time applications. FPGAs, on the other hand, have become true signal processing platforms due to their lightweight, low power consumption and massive parallel computational resources. This paper describes an FPGA-based hardware architecture that accelerates an object classification cortical model, HMAX. Compared to a CPU implementation, this hardware accelerator offers 23X (89X) speedup when mapped to a single-FPGA (multi-FPGA) platform, while maintaining a classification accuracy of 92.5%.

Original languageEnglish
Title of host publication2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings
Pages355-360
Number of pages6
DOIs
Publication statusPublished - 2011
Event2011 IEEE Workshop on Signal Processing Systems, SiPS 2011 - Beirut, Lebanon
Duration: Oct 4 2011Oct 7 2011

Other

Other2011 IEEE Workshop on Signal Processing Systems, SiPS 2011
CountryLebanon
CityBeirut
Period10/4/1110/7/11

Fingerprint

Field programmable gate arrays (FPGA)
Hardware
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Computer vision
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Signal processing
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Processing

Keywords

  • FPGA
  • Hardware
  • Neuromorphic Hardware Architecture
  • Neuromorphic vision algorithms
  • Signal Processing

ASJC Scopus subject areas

  • Signal Processing

Cite this

Maashri, A. A., DeBole, M., Yu, C. L., Narayanan, V., & Chakrabarti, C. (2011). A hardware architecture for accelerating neuromorphic vision algorithms. In 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings (pp. 355-360). [6089002] https://doi.org/10.1109/SiPS.2011.6089002

A hardware architecture for accelerating neuromorphic vision algorithms. / Maashri, A. Al; DeBole, M.; Yu, C. L.; Narayanan, V.; Chakrabarti, C.

2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings. 2011. p. 355-360 6089002.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Maashri, AA, DeBole, M, Yu, CL, Narayanan, V & Chakrabarti, C 2011, A hardware architecture for accelerating neuromorphic vision algorithms. in 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings., 6089002, pp. 355-360, 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Beirut, Lebanon, 10/4/11. https://doi.org/10.1109/SiPS.2011.6089002
Maashri AA, DeBole M, Yu CL, Narayanan V, Chakrabarti C. A hardware architecture for accelerating neuromorphic vision algorithms. In 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings. 2011. p. 355-360. 6089002 https://doi.org/10.1109/SiPS.2011.6089002
Maashri, A. Al ; DeBole, M. ; Yu, C. L. ; Narayanan, V. ; Chakrabarti, C. / A hardware architecture for accelerating neuromorphic vision algorithms. 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings. 2011. pp. 355-360
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