A BSP performance prediction model for parallel multigrid algorithms

B. O. Osoba; F. A. Rabhi; M. Ould-Khaoua

doi:10.1109/ICECS.2000.911566

A BSP performance prediction model for parallel multigrid algorithms

B. O. Osoba, F. A. Rabhi, M. Ould-Khaoua

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a BSP performance prediction model to support a programming environment for parallel multigrid algorithms. The model assists the user in the selection of the optimal problem parameters and directs the code generation scheme. Simulation experiments confirm that the model can be used asseful design tool to predict the optimal values of some numerical as well as implementation parameters for a given BSP architecture.

Original language	English
Title of host publication	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Pages	403-406
Number of pages	4
Volume	1
DOIs	https://doi.org/10.1109/ICECS.2000.911566
Publication status	Published - 2000
Event	7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000 - Jounieh, Lebanon Duration: Dec 17 2000 → Dec 20 2000

Other

Other	7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000
Country	Lebanon
City	Jounieh
Period	12/17/00 → 12/20/00

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICECS.2000.911566

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Cite this

Osoba, BO, Rabhi, FA & Ould-Khaoua, M 2000, A BSP performance prediction model for parallel multigrid algorithms. in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. vol. 1, 911566, pp. 403-406, 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, Jounieh, Lebanon, 12/17/00. https://doi.org/10.1109/ICECS.2000.911566

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