TY - JOUR
T1 - Performance evaluation of hypermeshes and meshes with wormhole routing
AU - Ould-Khaoua, M.
AU - Sotudeh, R.
PY - 1997
Y1 - 1997
N2 - The hypercube, which was widely used in early multicomputers, has fallen out of favour to be replaced by the 2-dimensional mesh or torus in recent multicomputers. This move was mainly influenced by Daily's study that has shown that for an equal implementation cost in VLSI the low-dimensional high-diameter mesh or torus has superior performance characteristics to the higher-dimensional low-diameter hypercube. Common networks such as the mesh, torus, and hypercube are graph topologies where a channel connects exactly two nodes. This paper argues that hypergraph topologies, where a channel can connect more than two nodes, represent a potential candidate for future high-performance multicomputer networks. A comparative analysis of a regular multi-dimensional hypergraph, referred to as the Distributed Crossbar Switch hypermesh (DCSH), and the mesh shows that the DCSH provides better performance for equal implementation costs in various technologies (e.g. VLSI and multiple-chip technology).
AB - The hypercube, which was widely used in early multicomputers, has fallen out of favour to be replaced by the 2-dimensional mesh or torus in recent multicomputers. This move was mainly influenced by Daily's study that has shown that for an equal implementation cost in VLSI the low-dimensional high-diameter mesh or torus has superior performance characteristics to the higher-dimensional low-diameter hypercube. Common networks such as the mesh, torus, and hypercube are graph topologies where a channel connects exactly two nodes. This paper argues that hypergraph topologies, where a channel can connect more than two nodes, represent a potential candidate for future high-performance multicomputer networks. A comparative analysis of a regular multi-dimensional hypergraph, referred to as the Distributed Crossbar Switch hypermesh (DCSH), and the mesh shows that the DCSH provides better performance for equal implementation costs in various technologies (e.g. VLSI and multiple-chip technology).
KW - Graphs
KW - Hypergraphs
KW - Hypermeshes
KW - Interconnection networks
KW - Meshes
KW - Message latency
KW - Multicomputers
KW - Queueing theory
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U2 - 10.1016/S1383-7621(96)00076-8
DO - 10.1016/S1383-7621(96)00076-8
M3 - Article
AN - SCOPUS:0031101195
SN - 1383-7621
VL - 43
SP - 345
EP - 353
JO - Journal of Systems Architecture
JF - Journal of Systems Architecture
IS - 1-5
ER -